fpga: xilinx: zynqmp: Add PL bitstream dowload support for ZynqMP

Add PL bitstream dowload support for ZynqMP
Bitstream  will be validated by uboot and loaded
to PL  by invoking an smc instruction to arm trusted
firmware, it will takecare of loading it to PL

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 6aa24d43590b68e24851cdc9919dab887e2a16de..dc62c62f6f370d470f5294b7f965e04f5ff668e5 100644 (file)
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
 obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
 obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
 obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
+obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
 obj-$(CONFIG_FPGA_XILINX) += xilinx.o
 obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
 ifdef CONFIG_FPGA_ALTERA

diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index d459a2f7a572180954bdc34a82fcf39c32be868e..2cd0104d8b154b35f8c85de42e50028ad614d57a 100644 (file)
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -199,6 +199,9 @@ int xilinx_info(xilinx_desc *desc)
                case xilinx_zynq:
                        printf("Zynq PL\n");
                        break;
+               case xilinx_zynqmp:
+                       printf("ZynqMP PL\n");
+                       break;
                        /* Add new family types here */
                default:
                        printf ("Unknown family type, %d\n", desc->family);
@@ -227,6 +230,9 @@ int xilinx_info(xilinx_desc *desc)
                case devcfg:
                        printf("Device configuration interface (Zynq)\n");
                        break;
+               case csu_dma:
+                       printf("csu_dma configuration interface (ZynqMP)\n");
+                       break;
                        /* Add new interface types here */
                default:
                        printf ("Unsupported interface type, %d\n", desc->iface);

diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
new file mode 100644 (file)
index 0000000..52df36e
--- /dev/null
+++ b/drivers/fpga/zynqmppl.c
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2015 - 2016, Xilinx, Inc,
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <console.h>
+#include <common.h>
+#include <zynqmppl.h>
+#include <asm/smc.h>
+#include <linux/sizes.h>
+
+#define DUMMY_WORD     0xffffffff
+
+/* Xilinx binary format header */
+static const u32 bin_format[] = {
+       DUMMY_WORD, /* Dummy words */
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       0x000000bb, /* Sync word */
+       0x11220044, /* Sync word */
+       DUMMY_WORD,
+       DUMMY_WORD,
+       0xaa995566, /* Sync word */
+};
+
+#define SWAP_NO                1
+#define SWAP_DONE      2
+
+/*
+ * Load the whole word from unaligned buffer
+ * Keep in your mind that it is byte loading on little-endian system
+ */
+static u32 load_word(const void *buf, u32 swap)
+{
+       u32 word = 0;
+       u8 *bitc = (u8 *)buf;
+       int p;
+
+       if (swap == SWAP_NO) {
+               for (p = 0; p < 4; p++) {
+                       word <<= 8;
+                       word |= bitc[p];
+               }
+       } else {
+               for (p = 3; p >= 0; p--) {
+                       word <<= 8;
+                       word |= bitc[p];
+               }
+       }
+
+       return word;
+}
+
+static u32 check_header(const void *buf)
+{
+       u32 i, pattern;
+       int swap = SWAP_NO;
+       u32 *test = (u32 *)buf;
+
+       debug("%s: Let's check bitstream header\n", __func__);
+
+       /* Checking that passing bin is not a bitstream */
+       for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
+               pattern = load_word(&test[i], swap);
+
+               /*
+                * Bitstreams in binary format are swapped
+                * compare to regular bistream.
+                * Do not swap dummy word but if swap is done assume
+                * that parsing buffer is binary format
+                */
+               if ((__swab32(pattern) != DUMMY_WORD) &&
+                   (__swab32(pattern) == bin_format[i])) {
+                       swap = SWAP_DONE;
+                       debug("%s: data swapped - let's swap\n", __func__);
+               }
+
+               debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
+                     &test[i], pattern, bin_format[i]);
+       }
+       debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
+             buf, swap == SWAP_NO ? "without" : "with");
+
+       return swap;
+}
+
+static void *check_data(u8 *buf, size_t bsize, u32 *swap)
+{
+       u32 word, p = 0; /* possition */
+
+       /* Because buf doesn't need to be aligned let's read it by chars */
+       for (p = 0; p < bsize; p++) {
+               word = load_word(&buf[p], SWAP_NO);
+               debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
+
+               /* Find the first bitstream dummy word */
+               if (word == DUMMY_WORD) {
+                       debug("%s: Found dummy word at position %x/%px\n",
+                             __func__, p, &buf[p]);
+                       *swap = check_header(&buf[p]);
+                       if (*swap) {
+                               /* FIXME add full bitstream checking here */
+                               return &buf[p];
+                       }
+               }
+               /* Loop can be huge - support CTRL + C */
+               if (ctrlc())
+                       return NULL;
+       }
+       return NULL;
+}
+
+static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
+{
+       u32 *new_buf;
+       u32 i;
+
+       if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
+               new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
+
+               /*
+                * This might be dangerous but permits to flash if
+                * ARCH_DMA_MINALIGN is greater than header size
+                */
+               if (new_buf > (u32 *)buf) {
+                       debug("%s: Aligned buffer is after buffer start\n",
+                             __func__);
+                       new_buf -= ARCH_DMA_MINALIGN;
+               }
+               printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
+                      buf, new_buf, swap);
+
+               for (i = 0; i < (len/4); i++)
+                       new_buf[i] = load_word(&buf[i], swap);
+
+               buf = new_buf;
+       } else if (swap != SWAP_DONE) {
+               /* For bitstream which are aligned */
+               u32 *new_buf = (u32 *)buf;
+
+               printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+                      swap);
+
+               for (i = 0; i < (len/4); i++)
+                       new_buf[i] = load_word(&buf[i], swap);
+       }
+
+       return (ulong)buf;
+}
+
+static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
+                                  size_t bsize, u32 blocksize, u32 *swap)
+{
+       ulong *buf_start;
+       ulong diff;
+
+       buf_start = check_data((u8 *)buf, blocksize, swap);
+
+       if (!buf_start)
+               return FPGA_FAIL;
+
+       /* Check if data is postpone from start */
+       diff = (ulong)buf_start - (ulong)buf;
+       if (diff) {
+               printf("%s: Bitstream is not validated yet (diff %lx)\n",
+                      __func__, diff);
+               return FPGA_FAIL;
+       }
+
+       if ((ulong)buf < SZ_1M) {
+               printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
+                      __func__, buf);
+               return FPGA_FAIL;
+       }
+
+       return 0;
+}
+
+static int zynqmp_info(xilinx_desc *desc)
+{
+       debug("%s called!\n", __func__);
+       return invoke_smc(ZYNQMP_SIP_SVC_CSU_DMA_INFO, 0, 0, 0);
+}
+
+static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
+                    bitstream_type bstype)
+{
+       u32 swap;
+       ulong bin_buf;
+
+       if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
+               return FPGA_FAIL;
+
+       bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
+
+       debug("%s called!\n", __func__);
+       flush_dcache_range(bin_buf, bin_buf + bsize);
+       return invoke_smc(ZYNQMP_SIP_SVC_CSU_DMA_LOAD, bin_buf, bsize, bstype);
+}
+
+static int zynqmp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+{
+       debug("%s called!\n", __func__);
+       return invoke_smc(ZYNQMP_SIP_SVC_CSU_DMA_DUMP, (u64)buf, bsize, 0);
+}
+
+struct xilinx_fpga_op zynqmp_op = {
+       .load = zynqmp_load,
+       .dump = zynqmp_dump,
+       .info = zynqmp_info,
+};

diff --git a/include/xilinx.h b/include/xilinx.h
index aebcb3bfdf29d7f87e4701fd01387bfe8f95b34a..d2a2ea71e1211a4b8382c3ec29297e86b9288984 100644 (file)
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -21,6 +21,7 @@ typedef enum {                        /* typedef xilinx_iface */
        master_selectmap,       /* master SelectMap (virtex2)           */
        slave_selectmap,        /* slave SelectMap (virtex2)            */
        devcfg,                 /* devcfg interface (zynq) */
+       csu_dma,                /* csu_dma interface (zynqmp) */
        max_xilinx_iface_type   /* insert all new types before this */
 } xilinx_iface;                        /* end, typedef xilinx_iface */
 
@@ -31,6 +32,7 @@ typedef enum {                        /* typedef xilinx_family */
        xilinx_virtex2,         /* Virtex2 Family */
        xilinx_spartan3,        /* Spartan-III Family */
        xilinx_zynq,            /* Zynq Family */
+       xilinx_zynqmp,          /* ZynqMP Family */
        max_xilinx_type         /* insert all new types before this */
 } xilinx_family;               /* end, typedef xilinx_family */
 

diff --git a/include/zynqmppl.h b/include/zynqmppl.h
new file mode 100644 (file)
index 0000000..67bf7c4
--- /dev/null
+++ b/include/zynqmppl.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2015 Xilinx, Inc,
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef _ZYNQMPPL_H_
+#define _ZYNQMPPL_H_
+
+#include <xilinx.h>
+
+#define ZYNQMP_SIP_SVC_CSU_DMA_INFO            0x82002004
+#define ZYNQMP_SIP_SVC_CSU_DMA_LOAD            0x82002005
+#define ZYNQMP_SIP_SVC_CSU_DMA_DUMP            0x82002006
+
+extern struct xilinx_fpga_op zynqmp_op;
+
+#define XILINX_ZYNQMP_DESC \
+{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, "xczu9eg" }
+
+#endif /* _ZYNQMPPL_H_ */