aarch64: return scalar fp8 values in fp registers

According to the aapcs64: If the argument is an 8-bit (...) precision
Floating-point or short vector type and the NSRN is less than 8, then the
argument is allocated to the least significant bits of register v[NSRN].

gcc/
	* config/aarch64/aarch64.cc
	(aarch64_vfp_is_call_or_return_candidate): use fp registers to
	return svmfloat8_t parameters.

gcc/testsuite/
	* gcc.target/aarch64/fp8_scalar_1.c:

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index e9cee0aa58013dea1459017baaaa343158f26f04..00bcf18ae97cea94227c00798b7951daa255d360 100644 (file)
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -22306,7 +22306,8 @@ aarch64_vfp_is_call_or_return_candidate (machine_mode mode,
 
   if ((!composite_p
        && (GET_MODE_CLASS (mode) == MODE_FLOAT
-          || GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT))
+          || GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT
+          || (type && TYPE_MAIN_VARIANT (type) == aarch64_mfp8_type_node)))
       || aarch64_short_vector_p (type, mode))
     {
       *count = 1;

diff --git a/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c b/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c
index 1bc2ac26b2a8a614bbcceb16446f0076d66980dc..61edf06401b81b26d51991d819fdd8664d180e97 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c
@@ -7,10 +7,10 @@
 
 /*
 **stacktest1:
+**     umov    w0, v0.b\[0\]
 **     sub     sp, sp, #16
-**     and     w0, w0, 255
 **     strb    w0, \[sp, 15\]
-**     ldrb    w0, \[sp, 15\]
+**     ldr     b0, \[sp, 15\]
 **     add     sp, sp, 16
 **     ret
 */