arm64: dts: ti: k3-j721s2-common-proc-board: Enable DisplayPort-1

Enable DSI display for J721S2 EVM.

Add the endpoint nodes to describe connection from:
DSS => DSI Bridge => DSI to eDP bridge => DisplayPort-1

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Tested-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250716060114.52122-7-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 793d50344fade0deb5ef5ece9ec0f7eda876b731..9e43dcff8ef22a11dda8d24e0784c61e3ff700e3 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -93,6 +93,28 @@
                         <3300000 0x1>;
        };
 
+       dp1_pwr_3v3: regulator-dp1-prw {
+               compatible = "regulator-fixed";
+               regulator-name = "dp1-pwr";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */
+               enable-active-high;
+       };
+
+       dp1: connector-dp1 {
+               compatible = "dp-connector";
+               label = "DP1";
+               type = "full-size";
+               dp-pwr-supply = <&dp1_pwr_3v3>;
+
+               port {
+                       dp1_connector_in: endpoint {
+                               remote-endpoint = <&dp1_out>;
+                       };
+               };
+       };
+
        transceiver1: can-phy1 {
                compatible = "ti,tcan1043";
                #phy-cells = <0>;
@@ -563,3 +585,74 @@
        pinctrl-0 = <&main_mcan5_pins_default>;
        phys = <&transceiver4>;
 };
+
+&dss {
+       /*
+        * DSS on J721S2-EVM supports DP on VP0 and DSI on VP2.
+        * These clock assignments are chosen to enable the following outputs:
+        * VP0 - DisplayPort SST
+        * VP2 - DSI
+        */
+       status = "okay";
+       assigned-clocks = <&k3_clks 158 2>,
+                         <&k3_clks 158 14>;
+       assigned-clock-parents = <&k3_clks 158 3>,
+                                <&k3_clks 158 16>;
+};
+
+&dss_ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       port@2 {
+               reg = <2>;
+
+               dpi2_out: endpoint {
+                       remote-endpoint = <&dsi0_in>;
+               };
+       };
+};
+
+&dsi0_ports {
+       port@0 {
+               reg = <0>;
+
+               dsi0_out: endpoint {
+                       remote-endpoint = <&dp1_in>;
+               };
+       };
+
+       port@1 {
+               reg = <1>;
+
+               dsi0_in: endpoint {
+                       remote-endpoint = <&dpi2_out>;
+               };
+       };
+};
+
+&dsi_edp_bridge_ports {
+       port@0 {
+               reg = <0>;
+
+               dp1_in: endpoint {
+                       remote-endpoint = <&dsi0_out>;
+               };
+       };
+
+       port@1 {
+               reg = <1>;
+
+               dp1_out: endpoint {
+                       remote-endpoint = <&dp1_connector_in>;
+               };
+       };
+};
+
+&dphy_tx0 {
+       status = "okay";
+};
+
+&dsi0 {
+       status = "okay";
+};