drm/xe: Extend Wa_14026781792 for xe3lpg

Wa_14026781792 applies to all graphics versions from 30.00
through 35.10 (inclusive). Since there are no IPs between
30.05 and 35.10, consolidate the RTP rules into a single
GRAPHICS_VERSION_RANGE(3000, 3510).

v2: (Matt)
 - There are no IPs between 30.05 and 35.10 either,
   So, consolidate this into a single GRAPHICS_VERSION_RANGE(3000, 3510)
 - Also move it up to the top part of the table

Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260317080059.1275116-2-nitin.r.gote@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 1d77f5b6401f39e1a88c485b08d70791a9d5bc52..a02ee1282d35b9461d61ba54481515cf5178b98e 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -656,6 +656,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
        },
+       { XE_RTP_NAME("14026781792"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3510), ENGINE_CLASS(RENDER)),
+         XE_RTP_ACTIONS(SET(FF_MODE, DIS_TE_PATCH_CTRL))
+       },
 
        /* DG1 */
 
@@ -784,10 +788,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
                       ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
        },
-       { XE_RTP_NAME("14026781792"),
-         XE_RTP_RULES(GRAPHICS_VERSION(3510), ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(FF_MODE, DIS_TE_PATCH_CTRL))
-       },
 };
 
 static __maybe_unused const struct xe_rtp_entry oob_was[] = {