net: gem: Fix gem driver on 1Gbps LAN

The whole driver used 100Mbps because of zc702 rev B.

Signed-off-by: Michal Simek <monstr@monstr.eu>

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 46801c791903efcd36167d267a70be0b1ec978c8..df429845d8b179a97424a0bbae15324dfa7351f3 100644 (file)
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -284,6 +284,23 @@ static int m88e1111s_config(struct phy_device *phydev)
        return 0;
 }
 
+/* Marvell 88E1116 */
+static int m88e1116_config(struct phy_device *phydev)
+{
+       /* Change Page Number */
+       phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
+       /* Delay RGMII TX and RX */
+       phy_write(phydev, MDIO_DEVAD_NONE, 21, 0x1070);
+       /* Change Page Number */
+       phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
+
+       genphy_config_aneg(phydev);
+
+       phy_reset(phydev);
+
+       return 0;
+}
+
 /* Marvell 88E1118 */
 static int m88e1118_config(struct phy_device *phydev)
 {
@@ -425,12 +442,12 @@ static struct phy_driver M88E1118_driver = {
        .shutdown = &genphy_shutdown,
 };
 
-static struct phy_driver M88E1118R_driver = {
-       .name = "Marvell 88E1118R",
+static struct phy_driver M88E1116R_driver = {
+       .name = "Marvell 88E1116R",
        .uid = 0x1410e40,
        .mask = 0xffffff0,
        .features = PHY_GBIT_FEATURES,
-       .config = &m88e1118_config,
+       .config = &m88e1116_config,
        .startup = &m88e1118_startup,
        .shutdown = &genphy_shutdown,
 };
@@ -481,7 +498,7 @@ int phy_marvell_init(void)
        phy_register(&M88E1145_driver);
        phy_register(&M88E1121R_driver);
        phy_register(&M88E1118_driver);
-       phy_register(&M88E1118R_driver);
+       phy_register(&M88E1116R_driver);
        phy_register(&M88E1111S_driver);
        phy_register(&M88E1011S_driver);
        phy_register(&M88E1518_driver);

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 89eed6f8cb73eb56730973d6b6e6c2b8e305c4b6..cd30498289abc86b81c7fe6aea5ad328a35eaa52 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -63,13 +63,14 @@
 #define ZYNQ_GEM_NWCTRL_MDEN_MASK      0x00000010 /* Enable MDIO port */
 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK   0x00000200 /* Start tx (tx_go) */
 
-#define ZYNQ_GEM_NWCFG_SPEED           0x00000001 /* 100 Mbps operation */
-#define ZYNQ_GEM_NWCFG_FDEN            0x00000002 /* Full Duplex mode */
-#define ZYNQ_GEM_NWCFG_FSREM           0x00020000 /* FCS removal */
+#define ZYNQ_GEM_NWCFG_SPEED100                0x000000001 /* 100 Mbps operation */
+#define ZYNQ_GEM_NWCFG_SPEED1000       0x000000400 /* 1Gbps operation */
+#define ZYNQ_GEM_NWCFG_FDEN            0x000000002 /* Full Duplex mode */
+#define ZYNQ_GEM_NWCFG_FSREM           0x000020000 /* FCS removal */
 #define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x000080000 /* Div pclk by 32, 80MHz */
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV2      0x0000c0000 /* Div pclk by 48, 120MHz */
 
-#define ZYNQ_GEM_NWCFG_INIT            (ZYNQ_GEM_NWCFG_SPEED | \
-                                       ZYNQ_GEM_NWCFG_FDEN | \
+#define ZYNQ_GEM_NWCFG_INIT            (ZYNQ_GEM_NWCFG_FDEN | \
                                        ZYNQ_GEM_NWCFG_FSREM | \
                                        ZYNQ_GEM_NWCFG_MDCCLKDIV)
 
@@ -338,26 +339,50 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
        /* Write RxBDs to IP */
        writel((u32) &(priv->rx_bd), &regs->rxqbase);
 
-       /* MAC Setup */
-       /* Setup Network Configuration register */
-       writel(ZYNQ_GEM_NWCFG_INIT, &regs->nwcfg);
-
        /* Setup for DMA Configuration register */
        writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
 
        /* Setup for Network Control register, MDIO, Rx and Tx enable */
-       setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK |
-                       ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK);
+       setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK );
 
 #ifdef CONFIG_PHYLIB
        /* interface - look at tsec */
        phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
 
-       phydev->supported &= supported;
+       phydev->supported = supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause;
        phydev->advertising = phydev->supported;
        priv->phydev = phydev;
        phy_config(phydev);
        phy_startup(phydev);
+
+       switch(phydev->speed) {
+       case SPEED_1000:
+               writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
+                                                               &regs->nwcfg);
+
+               /******* GEM0_CLK Setup *************************/
+               /* SLCR unlock */
+               *(volatile u32 *) 0xF8000008 = 0xDF0D;
+
+               /* Configure GEM0_RCLK_CTRL */
+               *(volatile u32 *) 0xF8000138 = (0 << 4) | (1 << 0);
+
+               /* Set divisors for appropriate frequency in GEM0_CLK_CTRL */
+               *(volatile u32 *) 0xF8000140 = (1 << 20) | (8 << 8) |
+                                               (0 << 4) | (1 << 0);
+
+               /* SLCR lock */
+               *(volatile u32 *) 0xF8000004 = 0x767B;
+
+               break;
+       case SPEED_100:
+               clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
+                       ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
+               break;
+       case SPEED_10:
+               break;
+       }
+
 #else
        /* PHY Setup */
 #ifdef CONFIG_EP107
@@ -401,8 +426,12 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
        puts("\nPHY claims autonegotiation complete...\n");
 
        puts("GEM link speed is 100Mbps\n");
+       writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, &regs->nwcfg);
 #endif
 
+       setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
+                                       ZYNQ_GEM_NWCTRL_TXEN_MASK);
+
        return 0;
 }
 
@@ -484,6 +513,10 @@ static int zynq_gem_recv(struct eth_device *dev)
 
 static void zynq_gem_halt(struct eth_device *dev)
 {
+       struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
+
+       clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
+                                               ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 }
 
 static int zynq_gem_miiphyread(const char *devname, uchar addr,