/* 8852C PCIE SCC */
.wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
- /* 8852B USB2.0/USB3.0 SCC */
- .wde_size25 = {RTW89_WDE_PG_64, 162, 94,},
+ /* 8852B USB2.0/USB3.0 SCC turbo */
+ .wde_size30 = {RTW89_WDE_PG_64, 220, 36,},
/* 8852C USB2.0 */
.wde_size31 = {RTW89_WDE_PG_64, 384, 0,},
/* PCIE */
.ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
.ple_size20_v1 = {RTW89_PLE_PG_128, 2554, 182, 40960,},
.ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,},
- /* 8852B USB2.0 SCC */
- .ple_size32 = {RTW89_PLE_PG_128, 620, 20,},
- /* 8852B USB3.0 SCC */
- .ple_size33 = {RTW89_PLE_PG_128, 632, 8,},
+ /* 8851B USB2.0 SCC turbo */
+ .ple_size27 = {RTW89_PLE_PG_128, 1396, 12,},
+ /* 8852B USB3.0 SCC turbo */
+ .ple_size31 = {RTW89_PLE_PG_128, 1392, 16,},
/* 8852C USB2.0 */
.ple_size34 = {RTW89_PLE_PG_128, 3374, 18,},
/* PCIE 64 */
.wde_qt18 = {3228, 60, 0, 40,},
.wde_qt19_v1 = {613, 6, 0, 20,},
.wde_qt23 = {958, 48, 0, 16,},
- /* 8852B USB2.0/USB3.0 SCC */
- .wde_qt25 = {152, 2, 0, 8,},
+ /* 8852B USB2.0/USB3.0 SCC turbo */
+ .wde_qt30 = {210, 2, 0, 8,},
/* 8852C USB2.0 */
.wde_qt31 = {338, 6, 0, 40,},
.ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,},
/* 8852A USB SCC */
.ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,},
.ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,},
+ /* 8852B USB3.0 SCC turbo */
+ .ple_qt27 = {1040, 0, 16, 48, 13, 13, 178, 0, 32, 14, 8, 0,},
+ .ple_qt28 = {1040, 0, 32, 48, 43, 13, 208, 0, 62, 14, 24, 0,},
/* USB 52C USB3.0 */
.ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
.ple_qt42_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,},
/* PCIE 64 */
.ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
.ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,},
- /* USB2.0 52B SCC */
- .ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,},
- /* USB2.0 52B 92K */
- .ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,},
- /* USB3.0 52B 92K */
- .ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,},
- .ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,},
+ /* 8851B USB2.0 SCC turbo */
+ .ple_qt61 = {858, 0, 16, 48, 4, 13, 370, 0, 32, 14, 8, 0, 0,},
+ .ple_qt62 = {858, 0, 32, 48, 37, 13, 403, 0, 65, 14, 24, 0, 0,},
/* USB2.0 52C */
.ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,},
/* USB2.0 52C */
{
u32 size = rtwdev->chip->fifo_size;
- if (mode == RTW89_QTA_SCC)
+ if (mode == RTW89_QTA_SCC && rtwdev->hci.type != RTW89_HCI_TYPE_USB)
size -= rtwdev->chip->dle_scc_rsvd_size;
return size;
const struct rtw89_dle_size wde_size18_v1;
const struct rtw89_dle_size wde_size19;
const struct rtw89_dle_size wde_size23;
- const struct rtw89_dle_size wde_size25;
+ const struct rtw89_dle_size wde_size30;
const struct rtw89_dle_size wde_size31;
const struct rtw89_dle_size ple_size0;
const struct rtw89_dle_size ple_size1;
const struct rtw89_dle_size ple_size19;
const struct rtw89_dle_size ple_size20_v1;
const struct rtw89_dle_size ple_size22_v1;
- const struct rtw89_dle_size ple_size32;
- const struct rtw89_dle_size ple_size33;
+ const struct rtw89_dle_size ple_size27;
+ const struct rtw89_dle_size ple_size31;
const struct rtw89_dle_size ple_size34;
const struct rtw89_wde_quota wde_qt0;
const struct rtw89_wde_quota wde_qt1;
const struct rtw89_wde_quota wde_qt18;
const struct rtw89_wde_quota wde_qt19_v1;
const struct rtw89_wde_quota wde_qt23;
- const struct rtw89_wde_quota wde_qt25;
+ const struct rtw89_wde_quota wde_qt30;
const struct rtw89_wde_quota wde_qt31;
const struct rtw89_ple_quota ple_qt0;
const struct rtw89_ple_quota ple_qt1;
const struct rtw89_ple_quota ple_qt18;
const struct rtw89_ple_quota ple_qt25;
const struct rtw89_ple_quota ple_qt26;
+ const struct rtw89_ple_quota ple_qt27;
+ const struct rtw89_ple_quota ple_qt28;
const struct rtw89_ple_quota ple_qt42;
const struct rtw89_ple_quota ple_qt42_v2;
const struct rtw89_ple_quota ple_qt43;
const struct rtw89_ple_quota ple_qt57;
const struct rtw89_ple_quota ple_qt58;
const struct rtw89_ple_quota ple_qt59;
- const struct rtw89_ple_quota ple_qt72;
- const struct rtw89_ple_quota ple_qt73;
- const struct rtw89_ple_quota ple_qt74;
- const struct rtw89_ple_quota ple_qt75;
+ const struct rtw89_ple_quota ple_qt61;
+ const struct rtw89_ple_quota ple_qt62;
const struct rtw89_ple_quota ple_qt78;
const struct rtw89_ple_quota ple_qt79;
const struct rtw89_ple_quota ple_qt_52a_wow;
};
static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_usb[] = {
- {18, 152, grp_0}, /* ACH 0 */
- {18, 152, grp_0}, /* ACH 1 */
- {18, 152, grp_0}, /* ACH 2 */
- {18, 152, grp_0}, /* ACH 3 */
+ {18, 210, grp_0}, /* ACH 0 */
+ {18, 210, grp_0}, /* ACH 1 */
+ {18, 210, grp_0}, /* ACH 2 */
+ {18, 210, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
- {18, 152, grp_0}, /* B0MGQ */
- {18, 152, grp_0}, /* B0HIQ */
+ {18, 210, grp_0}, /* B0MGQ */
+ {18, 210, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0} /* FWCMDQ */
};
static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_usb = {
- 152, /* Group 0 */
+ 210, /* Group 0 */
0, /* Group 1 */
- 152, /* Public Max */
+ 210, /* Public Max */
0 /* WP threshold */
};
};
static const struct rtw89_dle_mem rtw8851b_dle_mem_usb2[] = {
- [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
- &rtw89_mac_size.ple_size32, &rtw89_mac_size.wde_qt25,
- &rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt72,
- &rtw89_mac_size.ple_qt73},
+ [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
+ &rtw89_mac_size.ple_size27, &rtw89_mac_size.wde_qt30,
+ &rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt61,
+ &rtw89_mac_size.ple_qt62},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
};
static const struct rtw89_dle_mem rtw8851b_dle_mem_usb3[] = {
- [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
- &rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
- &rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
- &rtw89_mac_size.ple_qt75},
+ [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
+ &rtw89_mac_size.ple_size31, &rtw89_mac_size.wde_qt30,
+ &rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt27,
+ &rtw89_mac_size.ple_qt28},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
};
static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_usb[] = {
- {18, 152, grp_0}, /* ACH 0 */
- {18, 152, grp_0}, /* ACH 1 */
- {18, 152, grp_0}, /* ACH 2 */
- {18, 152, grp_0}, /* ACH 3 */
+ {18, 210, grp_0}, /* ACH 0 */
+ {18, 210, grp_0}, /* ACH 1 */
+ {18, 210, grp_0}, /* ACH 2 */
+ {18, 210, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
- {18, 152, grp_0}, /* B0MGQ */
- {18, 152, grp_0}, /* B0HIQ */
+ {18, 210, grp_0}, /* B0MGQ */
+ {18, 210, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0} /* FWCMDQ */
};
static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_usb = {
- 152, /* Group 0 */
+ 210, /* Group 0 */
0, /* Group 1 */
- 152, /* Public Max */
+ 210, /* Public Max */
0 /* WP threshold */
};
};
static const struct rtw89_dle_mem rtw8852b_dle_mem_usb3[] = {
- [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
- &rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
- &rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
- &rtw89_mac_size.ple_qt75},
+ [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
+ &rtw89_mac_size.ple_size31, &rtw89_mac_size.wde_qt30,
+ &rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt27,
+ &rtw89_mac_size.ple_qt28},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,