arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC

As per the A1 datasheet add missing cache information to the Amlogic A1
SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-7-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index f7f25a10f409ada7ced686ac979effee74c99a03..27b68ed85c4c29cd024007c2a4461a3717046f07 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -27,6 +27,12 @@
                        compatible = "arm,cortex-a35";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
                };
@@ -36,6 +42,12 @@
                        compatible = "arm,cortex-a35";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
                };
@@ -44,6 +56,9 @@
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;
+                       cache-size = <0x80000>; /* L2. 512 KB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };