spi: cadence-quadspi: Abort read if dummy cycles required are too many

[ Upstream commit ceeda328edeeeeac7579e9dbf0610785a3b83d39 ]

The controller can only support up to 31 dummy cycles. If the command
requires more it falls back to using 31. This command is likely to fail
because the correct number of cycles are not waited upon. Rather than
silently issuing an incorrect command, fail loudly so the caller can get
a chance to find out the command can't be supported by the controller.

Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-3-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 7bef63947b29fb8b6e6a9ae10163c7aa63159ea7..97a5e1eaeefdfb6e1f4366c6047c53a557d8fb02 100644 (file)
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -475,7 +475,7 @@ static int cqspi_read_setup(struct spi_nor *nor)
        /* Setup dummy clock cycles */
        dummy_clk = nor->read_dummy;
        if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
-               dummy_clk = CQSPI_DUMMY_CLKS_MAX;
+               return -EOPNOTSUPP;
 
        if (dummy_clk / 8) {
                reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);