]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
memory: tegra: Group SoC specific fields
authorKetan Patil <ketanp@nvidia.com>
Thu, 26 Feb 2026 16:31:13 +0000 (16:31 +0000)
committerKrzysztof Kozlowski <krzk@kernel.org>
Sat, 7 Mar 2026 17:02:29 +0000 (18:02 +0100)
Introduce new SoC specific fields in tegra_mc_soc struct for high
address mask and error status type mask because Tegra264 has different
values for these than the existing devices. Error status registers
e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the
error. In order to obtain such type of error from error status
register, we use error status type mask. Similarly, these error status
registers have bits which indicate the higher address bits of the
address responsible for mc error. In order to obtain such higher
address, we use high address mask. Make this change to prepare for
adding MC interrupt support for Tegra264.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com
[krzk: Fix checkpatch warning]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
drivers/memory/tegra/mc.c
drivers/memory/tegra/mc.h
drivers/memory/tegra/tegra114.c
drivers/memory/tegra/tegra124.c
drivers/memory/tegra/tegra186.c
drivers/memory/tegra/tegra194.c
drivers/memory/tegra/tegra20.c
drivers/memory/tegra/tegra210.c
drivers/memory/tegra/tegra234.c
drivers/memory/tegra/tegra30.c
include/soc/tegra/mc.h

index 8114574374d5c7c36d74ab2084faf725eebc22ae..5d0d9b7fc53490db441bb20b012a0ddb61edf586 100644 (file)
@@ -658,9 +658,12 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
                                        addr = mc_ch_readl(mc, channel, addr_hi_reg);
                                else
                                        addr = mc_readl(mc, addr_hi_reg);
-                       } else {
+                       } else if (mc->soc->mc_addr_hi_mask) {
                                addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
-                                       MC_ERR_STATUS_ADR_HI_MASK);
+                                       mc->soc->mc_addr_hi_mask);
+                       } else {
+                               dev_err_ratelimited(mc->dev, "Unable to determine high address!");
+                               return IRQ_NONE;
                        }
                        addr <<= 32;
                }
@@ -685,11 +688,11 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
                        }
                }
 
-               type = (value & MC_ERR_STATUS_TYPE_MASK) >>
+               type = (value & mc->soc->mc_err_status_type_mask) >>
                       MC_ERR_STATUS_TYPE_SHIFT;
                desc = tegra_mc_error_names[type];
 
-               switch (value & MC_ERR_STATUS_TYPE_MASK) {
+               switch (value & mc->soc->mc_err_status_type_mask) {
                case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
                        perm[0] = ' ';
                        perm[1] = '[';
index 34ce03ebc51caea5b8742a253e8e2c11861f33da..b286c2558fd527a0198a7a687d3f4ab71a5be47e 100644 (file)
 
 #define MC_ERR_STATUS_TYPE_SHIFT                       28
 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE           (0x6 << 28)
-#define MC_ERR_STATUS_TYPE_MASK                                (0x7 << 28)
 
 #define MC_ERR_STATUS_ADR_HI_SHIFT                     20
-#define MC_ERR_STATUS_ADR_HI_MASK                      0x3
 
 #define MC_BROADCAST_CHANNEL                           ~0
 
index fffb28eea57f041b6f9764542743b05eee47daa7..3a061a2d881eae437909a0b72bbfbdcac6a18591 100644 (file)
@@ -1117,4 +1117,5 @@ const struct tegra_mc_soc tegra114_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra30_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
+       .mc_err_status_type_mask = (0x7 << 28),
 };
index 2cf733198782c20db8c885bffc71b9e7159f83e0..4d394889c1e92c89a170f999459e55321f549c9d 100644 (file)
@@ -1278,6 +1278,8 @@ const struct tegra_mc_soc tegra124_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra30_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
+       .mc_addr_hi_mask = 0x3,
+       .mc_err_status_type_mask = (0x7 << 28),
 };
 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
 
@@ -1313,5 +1315,7 @@ const struct tegra_mc_soc tegra132_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra30_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
+       .mc_addr_hi_mask = 0x3,
+       .mc_err_status_type_mask = (0x7 << 28),
 };
 #endif /* CONFIG_ARCH_TEGRA_132_SOC */
index eb1eaaffc79a82bf340023afb358c25d80be7bf1..94cad76c52ac84f32bf09aa8101121a9d04bdad9 100644 (file)
@@ -916,5 +916,7 @@ const struct tegra_mc_soc tegra186_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra30_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
+       .mc_addr_hi_mask = 0x3,
+       .mc_err_status_type_mask = (0x7 << 28),
 };
 #endif
index cb0e7886857d909bbbeffe9e87445649c55f47ab..38852b2a0f4480c10ca1404c5fde0390e54c9ddd 100644 (file)
@@ -1361,4 +1361,6 @@ const struct tegra_mc_soc tegra194_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra30_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
+       .mc_addr_hi_mask = 0x3,
+       .mc_err_status_type_mask = (0x7 << 28),
 };
index 6750b08d875fe9f931959a6e92ae8aa8a84a17fd..a5cc770437ae24d720d656301cc45ebd4b921e26 100644 (file)
@@ -784,4 +784,5 @@ const struct tegra_mc_soc tegra20_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra20_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra20_mc_irq_handlers),
+       .mc_err_status_type_mask = (0x7 << 28),
 };
index 8283601ab52cdac52658c706c101424671d9f4ab..aa606df8a67980076fbf6f134de029eec64b9d1a 100644 (file)
@@ -1290,4 +1290,6 @@ const struct tegra_mc_soc tegra210_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra30_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
+       .mc_addr_hi_mask = 0x3,
+       .mc_err_status_type_mask = (0x7 << 28),
 };
index 9586d7528fb702e83055cc114e478547c2dbe0e8..67d5d4e01a65bd447e40ac3332a4bc23379d27bb 100644 (file)
@@ -1155,4 +1155,6 @@ const struct tegra_mc_soc tegra234_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra30_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
+       .mc_addr_hi_mask = 0x3,
+       .mc_err_status_type_mask = (0x7 << 28),
 };
index ff89b907877216c0c69d30e31cf32a84fa3148af..8a26a2f204e9b925e3ae866fac80a938c27ef87e 100644 (file)
@@ -1403,4 +1403,5 @@ const struct tegra_mc_soc tegra30_mc_soc = {
        .regs = &tegra20_mc_regs,
        .handle_irq = tegra30_mc_irq_handlers,
        .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
+       .mc_err_status_type_mask = (0x7 << 28),
 };
index d07de04c0f337bcb65aeeade9eab67dd8029769a..b9b1763b10b5fce2da5e7fa0d8baa5b0b32cf07e 100644 (file)
@@ -217,6 +217,8 @@ struct tegra_mc_soc {
 
        const irq_handler_t *handle_irq;
        unsigned int num_interrupts;
+       unsigned int mc_addr_hi_mask;
+       unsigned int mc_err_status_type_mask;
 };
 
 struct tegra_mc {