pinctrl: qcom: eliza: Merge QUP1_SE4 lanes in groups

QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs. The
current driver exposes lanes 0, 1, 2 and 3 as independent functions.
However, since these are usually configured in pairs in devicetree,
it makes more sense to merge them into groups.

So merge the per-lane functions into qup1_se4_01 and qup1_se4_23, and list
both GPIO36 and GPIO37 in each function group.

Fixes: 4f5b1f4e770b ("pinctrl: qcom: eliza: Split QUP1_SE4 lanes")
Suggested-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>

diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c
index bcd69c79a6288936670a44f417d57ea9971684db..4a2ef7b2a28c3a4bdf27805bda95463cf7ff20b5 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-eliza.c
+++ b/drivers/pinctrl/qcom/pinctrl-eliza.c
@@ -544,10 +544,8 @@ enum eliza_functions {
        msm_mux_qup1_se2_l3_mira,
        msm_mux_qup1_se2_l3_mirb,
        msm_mux_qup1_se3,
-       msm_mux_qup1_se4_l0,
-       msm_mux_qup1_se4_l1,
-       msm_mux_qup1_se4_l2,
-       msm_mux_qup1_se4_l3,
+       msm_mux_qup1_se4_01,
+       msm_mux_qup1_se4_23,
        msm_mux_qup1_se5,
        msm_mux_qup1_se6,
        msm_mux_qup1_se6_l1_mira,
@@ -996,20 +994,12 @@ static const char *const qup1_se3_groups[] = {
        "gpio44", "gpio45", "gpio46", "gpio47",
 };
 
-static const char *const qup1_se4_l0_groups[] = {
-       "gpio36",
+static const char *const qup1_se4_01_groups[] = {
+       "gpio36", "gpio37",
 };
 
-static const char *const qup1_se4_l1_groups[] = {
-       "gpio37",
-};
-
-static const char *const qup1_se4_l2_groups[] = {
-       "gpio37",
-};
-
-static const char *const qup1_se4_l3_groups[] = {
-       "gpio36",
+static const char *const qup1_se4_23_groups[] = {
+       "gpio36", "gpio37",
 };
 
 static const char *const qup1_se5_groups[] = {
@@ -1312,10 +1302,8 @@ static const struct pinfunction eliza_functions[] = {
        MSM_PIN_FUNCTION(qup1_se2_l3_mira),
        MSM_PIN_FUNCTION(qup1_se2_l3_mirb),
        MSM_PIN_FUNCTION(qup1_se3),
-       MSM_PIN_FUNCTION(qup1_se4_l0),
-       MSM_PIN_FUNCTION(qup1_se4_l1),
-       MSM_PIN_FUNCTION(qup1_se4_l2),
-       MSM_PIN_FUNCTION(qup1_se4_l3),
+       MSM_PIN_FUNCTION(qup1_se4_01),
+       MSM_PIN_FUNCTION(qup1_se4_23),
        MSM_PIN_FUNCTION(qup1_se5),
        MSM_PIN_FUNCTION(qup1_se6),
        MSM_PIN_FUNCTION(qup1_se6_l1_mira),
@@ -1412,8 +1400,8 @@ static const struct msm_pingroup eliza_groups[] = {
        [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),
        [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),
        [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),
-       [36] = PINGROUP(36, qup1_se4_l0, qup1_se4_l3, ibi_i3c, _, _, _, _, _, _, _, _),
-       [37] = PINGROUP(37, qup1_se4_l1, qup1_se4_l2, ibi_i3c, _, _, _, _, _, _, _, _),
+       [36] = PINGROUP(36, qup1_se4_01, qup1_se4_23, ibi_i3c, _, _, _, _, _, _, _, _),
+       [37] = PINGROUP(37, qup1_se4_01, qup1_se4_23, ibi_i3c, _, _, _, _, _, _, _, _),
        [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),
        [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),
        [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),