/* An integer used to scale the timeout of test programs. */
#define TIMEOUTFACTOR 1
+/* Set to 1 if 64 bit atomics are supported. */
+#undef __HAVE_64B_ATOMICS 0
+
/*
\f */
fi
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for 64-bit atomic support" >&5
+printf %s "checking for 64-bit atomic support... " >&6; }
+if test ${libc_cv_gcc_has_64b_atomics+y}
+then :
+ printf %s "(cached) " >&6
+else case e in #(
+ e) cat > conftest.c <<\EOF
+typedef struct { long long t; } X;
+extern void has_64b_atomics(void);
+void f(void)
+{
+ X x;
+ /* Use address of structure with 64-bit type. This avoids incorrect
+ implementations which return true even if long long is not 64-bit aligned.
+ This works on GCC and LLVM - other cases have bugs and they disagree. */
+ _Static_assert (__atomic_always_lock_free (sizeof (x), &x), "no_64b_atomics");
+}
+EOF
+if { ac_try='${CC-cc} -O2 -S conftest.c'
+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; };
+then
+ libc_cv_gcc_has_64b_atomics=yes
+else
+ libc_cv_gcc_has_64b_atomics=no
+fi
+rm -f conftest* ;;
+esac
+fi
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $libc_cv_gcc_has_64b_atomics" >&5
+printf "%s\n" "$libc_cv_gcc_has_64b_atomics" >&6; }
+if test "$libc_cv_gcc_has_64b_atomics" = yes; then
+ printf "%s\n" "#define __HAVE_64B_ATOMICS 1" >>confdefs.h
+
+else
+ printf "%s\n" "#define __HAVE_64B_ATOMICS 0" >>confdefs.h
+
+ fi
+
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for redirection of built-in functions" >&5
printf %s "checking for redirection of built-in functions... " >&6; }
if test ${libc_cv_gcc_builtin_redirection+y}
AC_DEFINE(HAVE_BUILTIN_MEMSET)
fi
+AC_CACHE_CHECK(for 64-bit atomic support, libc_cv_gcc_has_64b_atomics, [dnl
+cat > conftest.c <<\EOF
+typedef struct { long long t; } X;
+extern void has_64b_atomics(void);
+void f(void)
+{
+ X x;
+ /* Use address of structure with 64-bit type. This avoids incorrect
+ implementations which return true even if long long is not 64-bit aligned.
+ This works on GCC and LLVM - other cases have bugs and they disagree. */
+ _Static_assert (__atomic_always_lock_free (sizeof (x), &x), "no_64b_atomics");
+}
+EOF
+dnl
+if AC_TRY_COMMAND([${CC-cc} -O2 -S conftest.c]);
+then
+ libc_cv_gcc_has_64b_atomics=yes
+else
+ libc_cv_gcc_has_64b_atomics=no
+fi
+rm -f conftest* ])
+if test "$libc_cv_gcc_has_64b_atomics" = yes; then
+ AC_DEFINE(__HAVE_64B_ATOMICS, 1)
+else
+ AC_DEFINE(__HAVE_64B_ATOMICS, 0)
+ fi
+
AC_CACHE_CHECK(for redirection of built-in functions, libc_cv_gcc_builtin_redirection, [dnl
cat > conftest.c <<\EOF
extern char *strstr (const char *, const char *) __asm ("my_strstr");
({ __typeof (x) __x; __asm ("" : "=r" (__x) : "0" (x)); __x; })
#endif
-/* This is equal to 1 iff the architecture supports 64b atomic operations. */
-#ifndef __HAVE_64B_ATOMICS
-#error Unable to determine if 64-bit atomics are present.
-#endif
-
/* The following functions are a subset of the atomic operations provided by
C11. Usually, a function named atomic_OP_MO(args) is equivalent to C11's
atomic_OP_explicit(args, memory_order_MO); exceptions noted below. */
#ifndef _AARCH64_ATOMIC_MACHINE_H
#define _AARCH64_ATOMIC_MACHINE_H 1
-#define __HAVE_64B_ATOMICS 1
#define ATOMIC_EXCHANGE_USES_CAS 0
#endif
#include <stdint.h>
-#define __HAVE_64B_ATOMICS 1
-
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1
#ifndef _ARC_BITS_ATOMIC_H
#define _ARC_BITS_ATOMIC_H 1
-#define __HAVE_64B_ATOMICS 0
-
/* ARC does have legacy atomic EX reg, [mem] instruction but the micro-arch
is not as optimal as LLOCK/SCOND specially for SMP. */
#define ATOMIC_EXCHANGE_USES_CAS 1
License along with the GNU C Library. If not, see
<https://www.gnu.org/licenses/>. */
-#define __HAVE_64B_ATOMICS 0
#define ATOMIC_EXCHANGE_USES_CAS 1
#ifndef __CSKY_ATOMIC_H_
#define __CSKY_ATOMIC_H_
-#define __HAVE_64B_ATOMICS 0
#define ATOMIC_EXCHANGE_USES_CAS 1
#endif /* atomic-machine.h */
#ifndef _ATOMIC_MACHINE_H
#define _ATOMIC_MACHINE_H 1
-#define __HAVE_64B_ATOMICS 0
-
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1
#ifndef _LINUX_LOONGARCH_BITS_ATOMIC_H
#define _LINUX_LOONGARCH_BITS_ATOMIC_H 1
-#define __HAVE_64B_ATOMICS (__loongarch_grlen >= 64)
#define ATOMIC_EXCHANGE_USES_CAS 0
#endif /* bits/atomic.h */
#define _M68K_ATOMIC_MACHINE_H 1
#if defined __mc68020__ || defined __mcoldfire__
-# define __HAVE_64B_ATOMICS 0
-
/* XXX Is this actually correct? */
# define ATOMIC_EXCHANGE_USES_CAS 1
#else
#include <sysdep.h>
-#define __HAVE_64B_ATOMICS 0
-
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1
#define MIPS_PUSH_MIPS2
#endif
-#if _MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIN32
-#define __HAVE_64B_ATOMICS 0
-#else
-#define __HAVE_64B_ATOMICS 1
-#endif
-
/* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange
instruction which will be used by __atomic_exchange_n. */
#ifdef _MIPS_ARCH_XLP
#ifndef __OR1K_ATOMIC_H_
#define __OR1K_ATOMIC_H_
-#define __HAVE_64B_ATOMICS 0
#define ATOMIC_EXCHANGE_USES_CAS 1
#endif /* atomic-machine.h */
#ifndef _POWERPC_ATOMIC_MACHINE_H
#define _POWERPC_ATOMIC_MACHINE_H 1
-#if __WORDSIZE == 64
-# define __HAVE_64B_ATOMICS 1
-#else
-# define __HAVE_64B_ATOMICS 0
-#endif
#define ATOMIC_EXCHANGE_USES_CAS 1
/* Used on pthread_spin_{try}lock. */
#ifdef __riscv_atomic
-# define __HAVE_64B_ATOMICS (__riscv_xlen >= 64)
# define ATOMIC_EXCHANGE_USES_CAS 0
/* Miscellaneous. */
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#ifdef __s390x__
-# define __HAVE_64B_ATOMICS 1
-#else
-# define __HAVE_64B_ATOMICS 0
-#endif
-
#define ATOMIC_EXCHANGE_USES_CAS 1
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
-#define __HAVE_64B_ATOMICS 0
-
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1
#ifndef _ATOMIC_MACHINE_H
#define _ATOMIC_MACHINE_H 1
-#ifdef __arch64__
-# define __HAVE_64B_ATOMICS 1
-#else
-# define __HAVE_64B_ATOMICS 0
-#endif
-
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS __HAVE_64B_ATOMICS
#ifndef _X86_ATOMIC_MACHINE_H
#define _X86_ATOMIC_MACHINE_H 1
-#ifdef __x86_64__
-# define __HAVE_64B_ATOMICS 1
-#else
-/* Since the Pentium, i386 CPUs have supported 64-bit atomics, but the
- i386 psABI supplement provides only 4-byte alignment for uint64_t
- inside structs, so it is currently not possible to use 64-bit
- atomics on this platform. */
-# define __HAVE_64B_ATOMICS 0
-#endif
-
#define ATOMIC_EXCHANGE_USES_CAS 0
#define atomic_spin_nop() __asm ("pause")