ARM64: zynqmp: zcu102: dp: Use si570_1 for pixel clock

Enable the video clock from PL, and set phandle to si570_1.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts
index bb92d85b83f2076f8ce3a2d42f44679252b5a138..c0be327fb049a6aa855f959f43c62b6e13b79d23 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu102.dts
+++ b/arch/arm/dts/zynqmp-zcu102.dts
@@ -603,6 +603,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 
 &xilinx_drm {
        status = "okay";
+       clocks = <&si570_1>;
 };
 
 &xlnx_dp {
@@ -611,6 +612,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 
 &xlnx_dp_sub {
        status = "okay";
+       xlnx,vid-clk-pl;
 };
 
 &xlnx_dp_snd_pcm0 {