cpufreq: mediatek-hw: Refactor match data into struct

While the driver could get away with having the per-compatible match
data just be an array of the reg offsets, the only thing it used it for
right now, this doesn't really allow it to be extended in any meaningful
way if some other per-variant information needs to be communicated.

In preparation of adding support for hybrid "FDVFS" for MT8196, refactor
the code to make the DT match data a struct, which currently only
contains a single member: the reg offsets. This will allow this struct
to be extended with other members for other hardware variants.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c
index 74f1b4c796e4cc9ebccf50dd4e165a1eba03136a..b2aba1842226c7d24a8b9599ea62408cac9f803c 100644 (file)
--- a/drivers/cpufreq/mediatek-cpufreq-hw.c
+++ b/drivers/cpufreq/mediatek-cpufreq-hw.c
@@ -41,15 +41,22 @@ struct mtk_cpufreq_data {
        struct resource *res;
        void __iomem *base;
        int nr_opp;
+       const struct mtk_cpufreq_variant *variant;
 };
 
-static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] = {
-       [REG_FREQ_LUT_TABLE]    = 0x0,
-       [REG_FREQ_ENABLE]       = 0x84,
-       [REG_FREQ_PERF_STATE]   = 0x88,
-       [REG_FREQ_HW_STATE]     = 0x8c,
-       [REG_EM_POWER_TBL]      = 0x90,
-       [REG_FREQ_LATENCY]      = 0x110,
+struct mtk_cpufreq_variant {
+       const u16 reg_offsets[REG_ARRAY_SIZE];
+};
+
+static const struct mtk_cpufreq_variant cpufreq_mtk_base_variant = {
+       .reg_offsets = {
+               [REG_FREQ_LUT_TABLE]    = 0x0,
+               [REG_FREQ_ENABLE]       = 0x84,
+               [REG_FREQ_PERF_STATE]   = 0x88,
+               [REG_FREQ_HW_STATE]     = 0x8c,
+               [REG_EM_POWER_TBL]      = 0x90,
+               [REG_FREQ_LATENCY]      = 0x110,
+       },
 };
 
 static int __maybe_unused
@@ -157,7 +164,7 @@ static int mtk_cpu_create_freq_table(struct platform_device *pdev,
 
 static int mtk_cpu_resources_init(struct platform_device *pdev,
                                  struct cpufreq_policy *policy,
-                                 const u16 *offsets)
+                                 const struct mtk_cpufreq_variant *variant)
 {
        struct mtk_cpufreq_data *data;
        struct device *dev = &pdev->dev;
@@ -200,9 +207,10 @@ static int mtk_cpu_resources_init(struct platform_device *pdev,
 
        data->base = base;
        data->res = res;
+       data->variant = variant;
 
        for (i = REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++)
-               data->reg_bases[i] = base + offsets[i];
+               data->reg_bases[i] = base + variant->reg_offsets[i];
 
        ret = mtk_cpu_create_freq_table(pdev, data);
        if (ret) {
@@ -336,7 +344,7 @@ static void mtk_cpufreq_hw_driver_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id mtk_cpufreq_hw_match[] = {
-       { .compatible = "mediatek,cpufreq-hw", .data = &cpufreq_mtk_offsets },
+       { .compatible = "mediatek,cpufreq-hw", .data = &cpufreq_mtk_base_variant },
        {}
 };
 MODULE_DEVICE_TABLE(of, mtk_cpufreq_hw_match);