airoha: add nodes for 3rd PCIe line for AN7581

Some SoC might use the Serdes for the second USB port as a 3rd PCIe
line (with the SSTR register correctly setup).

Add the node for the 3rd PCIe card and enable for the eMMC RFB board.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/target/linux/airoha/dts/an7581-evb-emmc.dts b/target/linux/airoha/dts/an7581-evb-emmc.dts
index f7540f79e3762b3d9edc0f89bf85fd263eb8f78c..b814834c28ddc9c64bbad0a267d47848c963da57 100644 (file)
--- a/target/linux/airoha/dts/an7581-evb-emmc.dts
+++ b/target/linux/airoha/dts/an7581-evb-emmc.dts
@@ -57,6 +57,13 @@
                };
        };
 
+       pcie2_rst_pins: pcie2-rst-pins {
+               conf {
+                       pins = "pcie_reset2";
+                       drive-open-drain = <1>;
+               };
+       };
+
        gswp1_led0_pins: gswp1-led0-pins {
                mux {
                        function = "phy1_led0";
@@ -156,6 +163,12 @@
        status = "okay";
 };
 
+&pcie2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2_rst_pins>;
+       status = "okay";
+};
+
 &mdio {
        as21xx_1: ethernet-phy@1d {
                compatible = "ethernet-phy-ieee802.3-c45";

diff --git a/target/linux/airoha/dts/an7581.dtsi b/target/linux/airoha/dts/an7581.dtsi
index c0bf58f79585c3cc1e3ae9d01085d7419f8ffa00..83cf88e1cd9af3dc1eb3474c032ea57974757f69 100644 (file)
--- a/target/linux/airoha/dts/an7581.dtsi
+++ b/target/linux/airoha/dts/an7581.dtsi
@@ -718,6 +718,49 @@
                        };
                };
 
+               pcie2: pcie@1fc40000 {
+                       compatible = "airoha,en7581-pcie";
+                       device_type = "pci";
+                       linux,pci-domain = <2>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       reg = <0x0 0x1fc40000 0x0 0x1670>;
+                       reg-names = "pcie-mac";
+
+                       clocks = <&scuclk EN7523_CLK_PCIE>;
+                       clock-names = "sys-ck";
+
+                       phys = <&pciephy>;
+                       phy-names = "pcie-phy";
+
+                       ranges = <0x02000000 0 0x28000000 0x0 0x28000000 0 0x4000000>;
+
+                       resets = <&scuclk EN7581_PCIE0_RST>,
+                                <&scuclk EN7581_PCIE1_RST>,
+                                <&scuclk EN7581_PCIE2_RST>;
+                       reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
+
+                       mediatek,pbus-csr = <&pbus_csr 0x10 0x14>;
+
+                       interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                       bus-range = <0x00 0xff>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+                                       <0 0 0 2 &pcie_intc2 1>,
+                                       <0 0 0 3 &pcie_intc2 2>,
+                                       <0 0 0 4 &pcie_intc2 3>;
+
+                       status = "disabled";
+
+                       pcie_intc2: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
                npu: npu@1e900000 {
                        compatible = "airoha,en7581-npu";
                        reg = <0x0 0x1e900000 0x0 0x313000>;