pwm: tegra: fix pulse_width calculation

The pulse_width is expressed as N/256. A 100% duty cycle is only possible
when multiplied by 256 instead of 255.

Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>

diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c
index 4b57751f73f1718913c24519c8376125b0f915ad..4bbfeba8d986ccc6ef4a812dae5b79486b0e1f76 100644 (file)
--- a/drivers/pwm/tegra_pwm.c
+++ b/drivers/pwm/tegra_pwm.c
@@ -40,7 +40,7 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel,
                return -EINVAL;
        debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
 
-       pulse_width = duty_ns * 255 / period_ns;
+       pulse_width = duty_ns * 256 / period_ns;
 
        if (priv->polarity & BIT(channel))
                pulse_width = 256 - pulse_width;