atomic: Consolidate atomic_read_barrier implementation

All ABIs, except alpha, powerpc, and x86_64, define it to
atomic_full_barrier/__sync_synchronize, which can be mapped to
__atomic_thread_fence (__ATOMIC_SEQ_CST) in most cases, with the
exception of aarch64 (where the acquire fence is generated as
'dmb ishld' instead of 'dmb ish').

For s390x, it defaults to a memory barrier where __sync_synchronize
emits a 'bcr 15,0' (which the manual describes as pipeline
synchronization).

For PowerPC, it allows the use of lwsync for additional chips
(since _ARCH_PWR4 does not cover all chips that support it).

Tested on aarch64-linux-gnu, where the acquire produces a different
instruction that the current code.

Co-authored-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>

diff --git a/include/atomic.h b/include/atomic.h
index 227c4cdf27baae1c2a6e338fa7cbbd94cefc46ef..866c11c11f04def0c2802e577ca55cac77b975e7 100644 (file)
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -108,7 +108,7 @@
 
 
 #ifndef atomic_read_barrier
-# define atomic_read_barrier() atomic_full_barrier ()
+# define atomic_read_barrier() __atomic_thread_fence (__ATOMIC_ACQUIRE);
 #endif
 
 

diff --git a/sysdeps/alpha/atomic-machine.h b/sysdeps/alpha/atomic-machine.h
index a1d74a930e8a0a04dfec4a0bc764f410ea0c9f0d..198f5dc037cb7d6f923123e84647f40dd3de1721 100644 (file)
--- a/sysdeps/alpha/atomic-machine.h
+++ b/sysdeps/alpha/atomic-machine.h
@@ -22,5 +22,4 @@
 /* XXX Is this actually correct?  */
 #define ATOMIC_EXCHANGE_USES_CAS 1
 
-#define atomic_read_barrier()  __asm ("mb" : : : "memory");
 #define atomic_write_barrier() __asm ("wmb" : : : "memory");

diff --git a/sysdeps/generic/malloc-machine.h b/sysdeps/generic/malloc-machine.h
index 195fd8c5e6f6acf327c2751330915366fd100344..4fb8e809ccb7fa608b6edbf495498e7f10414687 100644 (file)
--- a/sysdeps/generic/malloc-machine.h
+++ b/sysdeps/generic/malloc-machine.h
@@ -22,10 +22,6 @@
 
 #include <atomic.h>
 
-#ifndef atomic_read_barrier
-# define atomic_read_barrier() atomic_full_barrier ()
-#endif
-
 #ifndef atomic_write_barrier
 # define atomic_write_barrier() atomic_full_barrier ()
 #endif

diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h
index 65c774a06404f091b6347737cc016987061c5726..e173b61e9cde70c6ed161299b89b52e4ad9429f8 100644 (file)
--- a/sysdeps/powerpc/atomic-machine.h
+++ b/sysdeps/powerpc/atomic-machine.h
@@ -37,23 +37,11 @@
 #endif
 
 #ifdef _ARCH_PWR4
-/*
- * Newer powerpc64 processors support the new "light weight" sync (lwsync)
- * So if the build is using -mcpu=[power4,power5,power5+,970] we can
- * safely use lwsync.
- */
-# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
 /*
  * "light weight" sync can also be used for the release barrier.
  */
 # define atomic_write_barrier()        __asm ("lwsync" ::: "memory")
 #else
-/*
- * Older powerpc32 processors don't support the new "light weight"
- * sync (lwsync).  So the only safe option is to use normal sync
- * for all powerpc32 applications.
- */
-# define atomic_read_barrier() __asm ("sync" ::: "memory")
 # define atomic_write_barrier()        __asm ("sync" ::: "memory")
 #endif
 

diff --git a/sysdeps/x86/atomic-machine.h b/sysdeps/x86/atomic-machine.h
index 97d9c99fa68310647ce4b0e8644a84bd09c1c19b..f46a0868e3ecc59902c92807e6bec6c7491463f5 100644 (file)
--- a/sysdeps/x86/atomic-machine.h
+++ b/sysdeps/x86/atomic-machine.h
@@ -31,7 +31,6 @@
 
 #define ATOMIC_EXCHANGE_USES_CAS       0
 
-#define atomic_read_barrier() __asm ("" ::: "memory")
 #define atomic_write_barrier() __asm ("" ::: "memory")
 
 #define atomic_spin_nop() __asm ("pause")