drm/amd/display: update pixel clock params after stream slice count change in context

[ Upstream commit cfab803884f426b36b58dbe1f86f99742767c208 ]

[why]
When ODM slice count is changed, otg master pipe's pixel clock params is
no longer valid as the value is dependent on ODM slice count.

Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: aa36d8971fcc ("drm/amd/display: Init link enc resources in dc_state only if res_pool presents")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ae275f1780d592d4d40065152b6c80106116d0e1..c16190a10883822c19d670111ad50b14cb2551e7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2237,7 +2237,7 @@ static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(
 }
 
 static bool update_pipe_params_after_odm_slice_count_change(
-               const struct dc_stream_state *stream,
+               struct pipe_ctx *otg_master,
                struct dc_state *context,
                const struct resource_pool *pool)
 {
@@ -2247,9 +2247,12 @@ static bool update_pipe_params_after_odm_slice_count_change(
 
        for (i = 0; i < pool->pipe_count && result; i++) {
                pipe = &context->res_ctx.pipe_ctx[i];
-               if (pipe->stream == stream && pipe->plane_state)
+               if (pipe->stream == otg_master->stream && pipe->plane_state)
                        result = resource_build_scaling_params(pipe);
        }
+
+       if (pool->funcs->build_pipe_pix_clk_params)
+               pool->funcs->build_pipe_pix_clk_params(otg_master);
        return result;
 }
 
@@ -2932,7 +2935,7 @@ bool resource_update_pipes_for_stream_with_slice_count(
                                        otg_master, new_ctx, pool);
        if (result)
                result = update_pipe_params_after_odm_slice_count_change(
-                               otg_master->stream, new_ctx, pool);
+                               otg_master, new_ctx, pool);
        return result;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 0a422fbb14bc84f95cbdf8dae267fb5d5f2ab46f..e73e597548375d5d22a2b964bfdd209b3f856293 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1273,15 +1273,19 @@ static void build_clamping_params(struct dc_stream_state *stream)
        stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
 }
 
-static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
+void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
 {
-
        get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
-
        pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-               pipe_ctx->clock_source,
-               &pipe_ctx->stream_res.pix_clk_params,
-               &pipe_ctx->pll_settings);
+                       pipe_ctx->clock_source,
+                       &pipe_ctx->stream_res.pix_clk_params,
+                       &pipe_ctx->pll_settings);
+}
+
+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
+{
+
+       dcn20_build_pipe_pix_clk_params(pipe_ctx);
 
        pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index 37ecaccc5d1281940a705be1277688297eb90d62..4cee3fa11a7ff46212cf07440bde537d2e02cc7f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -165,6 +165,7 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx,
 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);
 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);
+void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx);
 
 #endif /* __DC_RESOURCE_DCN20_H__ */
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 89b072447dba9b8be6f01bea239b96290e3fc76a..e940dd0f92b7365546900f6902dd6fcfe3854330 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2041,6 +2041,7 @@ static struct resource_funcs dcn32_res_pool_funcs = {
        .retain_phantom_pipes = dcn32_retain_phantom_pipes,
        .save_mall_state = dcn32_save_mall_state,
        .restore_mall_state = dcn32_restore_mall_state,
+       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
 };
 
 static uint32_t read_pipe_fuses(struct dc_context *ctx)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index f7de3eca1225abd33c3b6923ef657df253f0400d..4156a8cc2bc7e6036cbf841eb10175950f4582c1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1609,6 +1609,7 @@ static struct resource_funcs dcn321_res_pool_funcs = {
        .retain_phantom_pipes = dcn32_retain_phantom_pipes,
        .save_mall_state = dcn32_save_mall_state,
        .restore_mall_state = dcn32_restore_mall_state,
+       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
 };
 
 static uint32_t read_pipe_fuses(struct dc_context *ctx)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index b46cde52506699416df39ab6a27c6420dc791e1b..92e2ddc9ab7e20a87fcc3de14cb5ad2687e5bf52 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1237,15 +1237,11 @@ static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *contex
 {
        int i;
 
-       for (i = 0; i < table->odm_combine_count; i++) {
+       for (i = 0; i < table->odm_combine_count; i++)
                resource_update_pipes_for_stream_with_slice_count(context,
                                dc->current_state, dc->res_pool,
                                table->odm_combines[i].stream,
                                table->odm_combines[i].slice_count);
-               /* TODO: move this into the function above */
-               dcn20_build_mapped_resource(dc, context,
-                               table->odm_combines[i].stream);
-       }
 
        for (i = 0; i < table->mpc_combine_count; i++)
                resource_update_pipes_for_plane_with_slice_count(context,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index bac1420b1de84fc1ad0740eececead7f3333ca4f..10397d4dfb0753fb81f971b6280a0f9d817e5f23 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -205,6 +205,7 @@ struct resource_funcs {
        void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);
        void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config);
        void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config);
+       void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);
 };
 
 struct audio_support{