--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
-@@ -4353,6 +4353,29 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_C
- quirk_chelsio_T5_disable_root_port_attributes);
+@@ -4371,6 +4371,29 @@ static int pci_acs_ctrl_enabled(u16 acs_
+ }
/*
+ * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
* AMD has indicated that the devices below do not support peer-to-peer
* in any system where they are found in the southbridge with an AMD
* IOMMU in the system. Multifunction devices that do not support
-@@ -4763,6 +4786,8 @@ static const struct pci_dev_acs_enabled
+@@ -4772,6 +4795,8 @@ static const struct pci_dev_acs_enabled
{ PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
{ PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
{ PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
--- /dev/null
+From 3375590623e4a132b19a8740512f4deb95728933 Mon Sep 17 00:00:00 2001
+From: Raymond Pang <RaymondPang-oc@zhaoxin.com>
+Date: Fri, 27 Mar 2020 17:11:46 +0800
+Subject: PCI: Add Zhaoxin Vendor ID
+
+From: Raymond Pang <RaymondPang-oc@zhaoxin.com>
+
+commit 3375590623e4a132b19a8740512f4deb95728933 upstream.
+
+Add Zhaoxin Vendor ID to pci_ids.h
+
+Link: https://lore.kernel.org/r/20200327091148.5190-2-RaymondPang-oc@zhaoxin.com
+Signed-off-by: Raymond Pang <RaymondPang-oc@zhaoxin.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ include/linux/pci_ids.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2582,6 +2582,8 @@
+
+ #define PCI_VENDOR_ID_AMAZON 0x1d0f
+
++#define PCI_VENDOR_ID_ZHAOXIN 0x1d17
++
+ #define PCI_VENDOR_ID_HYGON 0x1d94
+
+ #define PCI_VENDOR_ID_HXT 0x1dbf
--- /dev/null
+From c8de8ed2dcaac82e5d76d467dc0b02e0ee79809b Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Thu, 5 Sep 2019 17:54:42 -0500
+Subject: PCI: Make ACS quirk implementations more uniform
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+commit c8de8ed2dcaac82e5d76d467dc0b02e0ee79809b upstream.
+
+The ACS quirks differ in needless ways, which makes them look more
+different than they really are.
+
+Reorder the ACS flags in order of definitions in the spec:
+
+ PCI_ACS_SV Source Validation
+ PCI_ACS_TB Translation Blocking
+ PCI_ACS_RR P2P Request Redirect
+ PCI_ACS_CR P2P Completion Redirect
+ PCI_ACS_UF Upstream Forwarding
+ PCI_ACS_EC P2P Egress Control
+ PCI_ACS_DT Direct Translated P2P
+
+(PCIe r5.0, sec 7.7.8.2) and use similar code structure in all. No
+functional change intended.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
+Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 41 +++++++++++++++++++----------------------
+ 1 file changed, 19 insertions(+), 22 deletions(-)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4422,18 +4422,18 @@ static bool pci_quirk_cavium_acs_match(s
+
+ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
+ {
++ if (!pci_quirk_cavium_acs_match(dev))
++ return -ENOTTY;
++
+ /*
+- * Cavium root ports don't advertise an ACS capability. However,
++ * Cavium Root Ports don't advertise an ACS capability. However,
+ * the RTL internally implements similar protection as if ACS had
+- * Request Redirection, Completion Redirection, Source Validation,
++ * Source Validation, Request Redirection, Completion Redirection,
+ * and Upstream Forwarding features enabled. Assert that the
+ * hardware implements and enables equivalent ACS functionality for
+ * these flags.
+ */
+- acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
+-
+- if (!pci_quirk_cavium_acs_match(dev))
+- return -ENOTTY;
++ acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+
+ return acs_flags ? 0 : 1;
+ }
+@@ -4451,7 +4451,7 @@ static int pci_quirk_xgene_acs(struct pc
+ }
+
+ /*
+- * Many Intel PCH root ports do provide ACS-like features to disable peer
++ * Many Intel PCH Root Ports do provide ACS-like features to disable peer
+ * transactions and validate bus numbers in requests, but do not provide an
+ * actual PCIe ACS capability. This is the list of device IDs known to fall
+ * into that category as provided by Intel in Red Hat bugzilla 1037684.
+@@ -4499,37 +4499,34 @@ static bool pci_quirk_intel_pch_acs_matc
+ return false;
+ }
+
+-#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
++#define INTEL_PCH_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
+
+ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+- u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
+- INTEL_PCH_ACS_FLAGS : 0;
+-
+ if (!pci_quirk_intel_pch_acs_match(dev))
+ return -ENOTTY;
+
+- return acs_flags & ~flags ? 0 : 1;
++ if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
++ acs_flags &= ~(INTEL_PCH_ACS_FLAGS);
++
++ return acs_flags ? 0 : 1;
+ }
+
+ /*
+- * These QCOM root ports do provide ACS-like features to disable peer
++ * These QCOM Root Ports do provide ACS-like features to disable peer
+ * transactions and validate bus numbers in requests, but do not provide an
+ * actual PCIe ACS capability. Hardware supports source validation but it
+ * will report the issue as Completer Abort instead of ACS Violation.
+- * Hardware doesn't support peer-to-peer and each root port is a root
+- * complex with unique segment numbers. It is not possible for one root
+- * port to pass traffic to another root port. All PCIe transactions are
+- * terminated inside the root port.
++ * Hardware doesn't support peer-to-peer and each Root Port is a Root
++ * Complex with unique segment numbers. It is not possible for one Root
++ * Port to pass traffic to another Root Port. All PCIe transactions are
++ * terminated inside the Root Port.
+ */
+ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+- u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
+- int ret = acs_flags & ~flags ? 0 : 1;
+-
+- pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
++ acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+
+- return ret;
++ return acs_flags ? 0 : 1;
+ }
+
+ static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
-@@ -5530,3 +5530,10 @@ static void pci_fixup_no_d0_pme(struct p
+@@ -5550,3 +5550,10 @@ static void pci_fixup_no_d0_pme(struct p
dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
--- /dev/null
+From 7cf2cba43f15c74bac46dc5f0326805d25ef514d Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Fri, 6 Sep 2019 18:36:06 -0500
+Subject: PCI: Unify ACS quirk desired vs provided checking
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+commit 7cf2cba43f15c74bac46dc5f0326805d25ef514d upstream.
+
+Most of the ACS quirks have a similar pattern of:
+
+ acs_flags &= ~( <controls provided by this device> );
+ return acs_flags ? 0 : 1;
+
+Pull this out into a helper function to simplify the quirks slightly. The
+helper function is also a convenient place for comments about what the list
+of ACS controls means. No functional change intended.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
+Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 67 ++++++++++++++++++++++++++++++++++-----------------
+ 1 file changed, 45 insertions(+), 22 deletions(-)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4353,6 +4353,24 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_C
+ quirk_chelsio_T5_disable_root_port_attributes);
+
+ /*
++ * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
++ * by a device
++ * @acs_ctrl_req: Bitmask of desired ACS controls
++ * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
++ * the hardware design
++ *
++ * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
++ * in @acs_ctrl_ena, i.e., the device provides all the access controls the
++ * caller desires. Return 0 otherwise.
++ */
++static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
++{
++ if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
++ return 1;
++ return 0;
++}
++
++/*
+ * AMD has indicated that the devices below do not support peer-to-peer
+ * in any system where they are found in the southbridge with an AMD
+ * IOMMU in the system. Multifunction devices that do not support
+@@ -4395,7 +4413,7 @@ static int pci_quirk_amd_sb_acs(struct p
+ /* Filter out flags not applicable to multifunction */
+ acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
+
+- return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
+ #else
+ return -ENODEV;
+ #endif
+@@ -4433,9 +4451,8 @@ static int pci_quirk_cavium_acs(struct p
+ * hardware implements and enables equivalent ACS functionality for
+ * these flags.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+ }
+
+ static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
+@@ -4445,9 +4462,8 @@ static int pci_quirk_xgene_acs(struct pc
+ * transactions with others, allowing masking out these bits as if they
+ * were unimplemented in the ACS capability.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+ }
+
+ /*
+@@ -4499,17 +4515,16 @@ static bool pci_quirk_intel_pch_acs_matc
+ return false;
+ }
+
+-#define INTEL_PCH_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
+-
+ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+ if (!pci_quirk_intel_pch_acs_match(dev))
+ return -ENOTTY;
+
+ if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
+- acs_flags &= ~(INTEL_PCH_ACS_FLAGS);
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags, 0);
+ }
+
+ /*
+@@ -4524,9 +4539,8 @@ static int pci_quirk_intel_pch_acs(struc
+ */
+ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+ }
+
+ static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
+@@ -4627,7 +4641,7 @@ static int pci_quirk_intel_spt_pch_acs(s
+
+ pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
+
+- return acs_flags & ~ctrl ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags, ctrl);
+ }
+
+ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
+@@ -4641,10 +4655,9 @@ static int pci_quirk_mf_endpoint_acs(str
+ * perform peer-to-peer with other functions, allowing us to mask out
+ * these bits as if they were unimplemented in the ACS capability.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
+- PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
++ PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
+ }
+
+ static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
+@@ -4655,9 +4668,8 @@ static int pci_quirk_brcm_acs(struct pci
+ * Allow each Root Port to be in a separate IOMMU group by masking
+ * SV/RR/CR/UF bits.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+ }
+
+ static const struct pci_dev_acs_enabled {
+@@ -4763,6 +4775,17 @@ static const struct pci_dev_acs_enabled
+ { 0 }
+ };
+
++/*
++ * pci_dev_specific_acs_enabled - check whether device provides ACS controls
++ * @dev: PCI device
++ * @acs_flags: Bitmask of desired ACS controls
++ *
++ * Returns:
++ * -ENOTTY: No quirk applies to this device; we can't tell whether the
++ * device provides the desired controls
++ * 0: Device does not provide all the desired controls
++ * >0: Device provides all the controls in @acs_flags
++ */
+ int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
+ {
+ const struct pci_dev_acs_enabled *i;
net-mlx5e-get-the-latest-values-from-counters-in-switchdev-mode.patch
pci-avoid-asmedia-xhci-usb-pme-from-d0-defect.patch
pci-add-acs-quirk-for-zhaoxin-multi-function-devices.patch
+pci-make-acs-quirk-implementations-more-uniform.patch
+pci-unify-acs-quirk-desired-vs-provided-checking.patch
+pci-add-zhaoxin-vendor-id.patch
pci-add-acs-quirk-for-zhaoxin-root-downstream-ports.patch
pci-move-apex-edge-tpu-class-quirk-to-fix-bar-assignment.patch
arm-dts-bcm283x-disable-dsi0-node.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
