#define VEX_S390X_MODEL_Z14_ZR1 15
#define VEX_S390X_MODEL_Z15 16
#define VEX_S390X_MODEL_Z16 17
-#define VEX_S390X_MODEL_UNKNOWN 18 /* always last in list */
+#define VEX_S390X_MODEL_Z17 18
+#define VEX_S390X_MODEL_UNKNOWN 19 /* always last in list */
#define VEX_S390X_MODEL_MASK 0x3F
#define VEX_HWCAPS_S390X_LDISP (1<<6) /* Long-displacement facility */
{ "8562", VEX_S390X_MODEL_Z15 },
{ "3931", VEX_S390X_MODEL_Z16 },
{ "3932", VEX_S390X_MODEL_Z16 },
+ { "9175", VEX_S390X_MODEL_Z17 },
};
Int model, n, fh;
bfp-XxC.vgtest bfp-XxC.stderr.exp bfp-XxC.post.exp \
ecag.stdout.exp-z10ec ecag.stdout.exp-z196 ecag.stdout.exp-zec12 \
ecag.stdout.exp-z13 ecag.stdout.exp-z14 ecag.stdout.exp-z15 \
- ecag.stdout.exp-z16 \
+ ecag.stdout.exp-z16 ecag.stdout.exp-z17 \
op00.stderr.exp op00.vgtest \
dfp-XxC.vgtest dfp-XxC.stderr.exp dfp-XxC.post.exp \
dfp-XiC.vgtest dfp-XiC.stderr.exp dfp-XiC.post.exp \
--- /dev/null
+L1 topology: separate data and instruction; private
+L1 cache line size data: 256
+L1 cache line size insn: 256
+L1 total cachesize data: 131072
+L1 total cachesize insn: 131072
+L1 set. assoc. data: 8
+L1 set. assoc. insn: 8
+L2 topology: unified data and instruction; private
+L2 cache line size data: 256
+L2 cache line size insn: 256
+L2 total cachesize data: 37748736
+L2 total cachesize insn: 37748736
+L2 set. assoc. data: 18
+L2 set. assoc. insn: 18
+L3 topology: unified data and instruction; shared
+L3 cache line size data: 256
+L3 cache line size insn: 256
+L3 total cachesize data: 377487360
+L3 total cachesize insn: 377487360
+L3 set. assoc. data: 180
+L3 set. assoc. insn: 180
{ "8562", "z15" },
{ "3931", "z16" },
{ "3932", "z16" },
+ { "9175", "z17" },
};