PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1
6 bit divider
- PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x9
+ PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc
000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
clock. This is not usually an issue, but designers must be aware.)
| 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
| 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010900U);
+ PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U);
/*############################################################################################################################ */
/*Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>
PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1
6 bit divider
- PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x6
+ PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3
000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2
This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000602U)
+ (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U)
RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK | 0 );
RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
- | 0x00000006U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
+ | 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
| 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
+ PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
/*############################################################################################################################ */
/*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC</p>
PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
/*############################################################################################################################ */
- /*Register : PCIE_REF_CTRL @ 0XFD1A00B4</p>
-
- 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
- es of the new clock. This is not usually an issue, but designers must be aware.)
- PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0
-
- Clock active signal. Switch to 0 to disable the clock
- PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1
-
- 6 bit divider
- PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2
-
- This register controls this reference clock
- (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U)
- RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK | 0 );
-
- RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
- | 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
- | 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
- /*############################################################################################################################ */
-
/*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070</p>
6 bit divider
tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next
nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks
- PSU_DDRC_DRAMTMG0_T_FAW 0xc
+ PSU_DDRC_DRAMTMG0_T_FAW 0x11
tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12
SDRAM Timing Register 0
- (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x110C2412U)
+ (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11112412U)
RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK | 0 );
RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT
- | 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT
+ | 0x00000011U << DDRC_DRAMTMG0_T_FAW_SHIFT
| 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
| 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U);
+ PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x11112412U);
/*############################################################################################################################ */
/*Register : DRAMTMG1 @ 0XFD070104</p>
tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
up to next integer value. Unit: Clocks.
- PSU_DDRC_DRAMTMG1_T_RC 0x19
+ PSU_DDRC_DRAMTMG1_T_RC 0x1a
SDRAM Timing Register 1
- (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x00040419U)
+ (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU)
RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK | 0 );
RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT
| 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT
- | 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT
+ | 0x0000001AU << DDRC_DRAMTMG1_T_RC_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U);
+ PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x0004041AU);
/*############################################################################################################################ */
/*Register : DRAMTMG2 @ 0XFD070108</p>
PSU_DDR_PHY_DTPR1_RESERVED_23 0x0
4-bank activate period
- PSU_DDR_PHY_DTPR1_TFAW 0x18
+ PSU_DDR_PHY_DTPR1_TFAW 0x22
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0
PSU_DDR_PHY_DTPR1_TMRD 0x8
DRAM Timing Parameters Register 1
- (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28180708U)
+ (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28220708U)
RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT
| 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT
| 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT
- | 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT
+ | 0x00000022U << DDR_PHY_DTPR1_TFAW_SHIFT
| 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
| 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT
| 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
| 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U);
+ PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28220708U);
/*############################################################################################################################ */
/*Register : DTPR2 @ 0XFD080118</p>
PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0
Activate to activate command delay (same bank)
- PSU_DDR_PHY_DTPR5_TRC 0x32
+ PSU_DDR_PHY_DTPR5_TRC 0x34
Reserved. Return zeroes on reads.
PSU_DDR_PHY_DTPR5_RESERVED_15 0x0
PSU_DDR_PHY_DTPR5_TWTR 0x9
DRAM Timing Parameters Register 5
- (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00320F09U)
+ (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00340F09U)
RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK | 0 );
RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
- | 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT
+ | 0x00000034U << DDR_PHY_DTPR5_TRC_SHIFT
| 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT
| 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT
| 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
| 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U);
+ PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00340F09U);
/*############################################################################################################################ */
/*Register : DTPR6 @ 0XFD080128</p>
Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
- PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 1
+ PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0
Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0
Configures MIO Pin 26 peripheral interface mapping
- (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000008U)
+ (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U)
RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
- | 0x00000001U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
+ | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
| 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000008U);
+ PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U);
/*############################################################################################################################ */
/*Register : MIO_PIN_27 @ 0XFF18006C</p>
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1
Master Tri-state Enable for pin 26, active high
- PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 1
+ PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0
Master Tri-state Enable for pin 27, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0
MIO pin Tri-state Enables, 31:0
- (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x56240000U)
+ (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U)
RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK | 0 );
RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
- | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
+ | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x56240000U);
+ PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U);
/*############################################################################################################################ */
/*Register : MIO_MST_TRI1 @ 0XFF180208</p>
// : FPD RESET
/*Register : RST_FPD_TOP @ 0XFD1A0100</p>
- PCIE config reset
- PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0
-
- PCIE control block level reset
- PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0
-
- PCIE bridge block level reset (AXI interface)
- PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0
-
Display Port block level reset (includes DPDMA)
PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0
PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0
FPD Block level software controlled reset
- (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U)
- RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 );
+ (OFFSET, MASK, VALUE) (0XFD1A0100, 0x0001807EU ,0x00000000U)
+ RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 );
- RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
- | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
- | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
- | 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+ RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
| 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
| 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
| 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
| 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
| 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U);
+ PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x0001807EU ,0x00000000U);
/*############################################################################################################################ */
// : SD
PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U);
/*############################################################################################################################ */
+ // : TPIU WIDTH
+ // : TRACE LOCK ACCESS REGISTER
+ /*Register : LAR @ 0XFE980FB0</p>
+
+ A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the a
+ fect of removing write access.
+ PSU_TPIU_LAR_ACCESS_W 0XC5ACCE55
+
+ This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject t
+ the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the compo
+ ent.
+ (OFFSET, MASK, VALUE) (0XFE980FB0, 0xFFFFFFFFU ,0xC5ACCE55U)
+ RegMask = (TPIU_LAR_ACCESS_W_MASK | 0 );
+
+ RegVal = ((0xC5ACCE55U << TPIU_LAR_ACCESS_W_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (TPIU_LAR_OFFSET ,0xFFFFFFFFU ,0xC5ACCE55U);
+ /*############################################################################################################################ */
+
+ // : TRACE CURRENT PORT SIZE
+ /*Register : Current_port_size @ 0XFE980004</p>
+
+ Indicates whether the current port size of the TPIU is 32 bits.
+ PSU_TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32 1
+
+ The Current Port Size Register has the same format as the Supported Port Sizes register but only one bit is set, and all othe
+ s must be zero. Writing values with more than one bit set or setting a bit that is not indicated as supported is not supporte
+ and causes unpredictable behavior.On reset this defaults to the smallest possible port size, 1 bit, and so reads as 0x000000
+ 1.Note : Do not modify the value while the Trace Port is still active, or without correctly stopping the formatter (see Forma
+ ter and Flush Control Register, 0x304). This can result in data not being aligned to the port width. For example, data on an
+ -bit Trace Port might not be byte aligned.
+ (OFFSET, MASK, VALUE) (0XFE980004, 0x80000000U ,0x80000000U)
+ RegMask = (TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_MASK | 0 );
+
+ RegVal = ((0x00000001U << TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (TPIU_CURRENT_PORT_SIZE_OFFSET ,0x80000000U ,0x80000000U);
+ /*############################################################################################################################ */
+
+ // : TRACE LOCK ACCESS REGISTER
+ /*Register : LAR @ 0XFE980FB0</p>
+
+ A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the a
+ fect of removing write access.
+ PSU_TPIU_LAR_ACCESS_W 0X0
+
+ This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject t
+ the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the compo
+ ent.
+ (OFFSET, MASK, VALUE) (0XFE980FB0, 0xFFFFFFFFU ,0x00000000U)
+ RegMask = (TPIU_LAR_ACCESS_W_MASK | 0 );
+
+ RegVal = ((0x00000000U << TPIU_LAR_ACCESS_W_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (TPIU_LAR_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+ /*############################################################################################################################ */
+
// : UART BAUD RATE
/*Register : Baud_rate_divider_reg0 @ 0XFF000034</p>
/*############################################################################################################################ */
// : CSU TAMPER RESPONSE
- // : AFIFM INTERFACE WIDTH
// : CPU QOS DEFAULT
/*Register : ACE_CTRL @ 0XFD5C0060</p>
// : APERTURE PERMISIION LIST
// : APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF
- /*Register : APERPERM_000 @ 0XFF981000</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_000_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_000_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_000_PARITY 0x0
-
- Entry 000 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00010000
- (OFFSET, MASK, VALUE) (0XFF981000, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_000_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_000_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_000_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_000_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_000_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_000_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_000_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF
- /*Register : APERPERM_001 @ 0XFF981004</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_001_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_001_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_001_PARITY 0x0
-
- Entry 001 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00010000
- (OFFSET, MASK, VALUE) (0XFF981004, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_001_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_001_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_001_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_001_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_001_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_001_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_001_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF
- /*Register : APERPERM_002 @ 0XFF981008</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_002_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_002_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_002_PARITY 0x0
-
- Entry 002 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00020000
- (OFFSET, MASK, VALUE) (0XFF981008, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_002_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_002_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_002_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_002_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_002_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_002_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_002_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF
- /*Register : APERPERM_003 @ 0XFF98100C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_003_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_003_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_003_PARITY 0x0
-
- Entry 003 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00030000
- (OFFSET, MASK, VALUE) (0XFF98100C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_003_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_003_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_003_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_003_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_003_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_003_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_003_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF
- /*Register : APERPERM_004 @ 0XFF981010</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_004_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_004_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_004_PARITY 0x0
-
- Entry 004 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00040000
- (OFFSET, MASK, VALUE) (0XFF981010, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_004_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_004_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_004_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_004_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_004_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_004_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_004_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF
- /*Register : APERPERM_005 @ 0XFF981014</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_005_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_005_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_005_PARITY 0x0
-
- Entry 005 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00050000
- (OFFSET, MASK, VALUE) (0XFF981014, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_005_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_005_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_005_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_005_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_005_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_005_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_005_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF
- /*Register : APERPERM_006 @ 0XFF981018</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_006_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_006_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_006_PARITY 0x0
-
- Entry 006 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00060000
- (OFFSET, MASK, VALUE) (0XFF981018, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_006_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_006_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_006_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_006_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_006_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_006_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_006_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF
- /*Register : APERPERM_007 @ 0XFF98101C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_007_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_007_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_007_PARITY 0x0
-
- Entry 007 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00070000
- (OFFSET, MASK, VALUE) (0XFF98101C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_007_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_007_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_007_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_007_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_007_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_007_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_007_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF
- /*Register : APERPERM_008 @ 0XFF981020</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_008_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_008_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_008_PARITY 0x0
-
- Entry 008 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00080000
- (OFFSET, MASK, VALUE) (0XFF981020, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_008_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_008_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_008_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_008_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_008_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_008_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_008_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF
- /*Register : APERPERM_009 @ 0XFF981024</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_009_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_009_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_009_PARITY 0x0
-
- Entry 009 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00090000
- (OFFSET, MASK, VALUE) (0XFF981024, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_009_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_009_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_009_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_009_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_009_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_009_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_009_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
// : APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF
- /*Register : APERPERM_010 @ 0XFF981028</p>
+ // : APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF
+ // : APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF
+ // : APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF
+ // : APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF
+ // : APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF
+ // : APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF
+ // : APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF
+ // : APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF
+ // : APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF
+ // : APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF
+ // : APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF
+ // : APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF
+ // : APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
+ // : APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF24FFFF
+ // : APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF
+ // : APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFFF
+ // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
+ // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
+ // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
+ // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
+ // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
+ // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
+ // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
+ // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
+ // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_048 @ 0XFF9810C0</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_010_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_048_PERMISSION 0x10
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_010_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_048_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_010_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_048_PARITY 0x0
- Entry 010 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x000A0000
- (OFFSET, MASK, VALUE) (0XFF981028, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_010_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_010_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_010_PARITY_MASK | 0 );
+ Entry 048 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00300000
+ (OFFSET, MASK, VALUE) (0XFF9810C0, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_048_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_010_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_010_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_010_PARITY_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_010_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_048_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- // : APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF
- /*Register : APERPERM_011 @ 0XFF98102C</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_049 @ 0XFF9810C4</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_011_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_049_PERMISSION 0x40
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_011_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_049_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_011_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_049_PARITY 0x0
- Entry 011 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x000B0000
- (OFFSET, MASK, VALUE) (0XFF98102C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_011_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_011_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_011_PARITY_MASK | 0 );
+ Entry 049 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00310000
+ (OFFSET, MASK, VALUE) (0XFF9810C4, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_049_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_011_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_011_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_011_PARITY_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_011_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_049_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- // : APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF
- /*Register : APERPERM_012 @ 0XFF981030</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_050 @ 0XFF9810C8</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_012_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_050_PERMISSION 0x80
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_012_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_050_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_012_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_050_PARITY 0x0
- Entry 012 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x000C0000
- (OFFSET, MASK, VALUE) (0XFF981030, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_012_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_012_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_012_PARITY_MASK | 0 );
+ Entry 050 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00320000
+ (OFFSET, MASK, VALUE) (0XFF9810C8, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_050_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_012_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_012_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_012_PARITY_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_012_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_050_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- // : APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF
- /*Register : APERPERM_013 @ 0XFF981034</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_051 @ 0XFF9810CC</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_013_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_051_PERMISSION 0x20
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_013_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_051_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_013_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_051_PARITY 0x0
- Entry 013 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x000D0000
- (OFFSET, MASK, VALUE) (0XFF981034, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_013_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_013_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_013_PARITY_MASK | 0 );
+ Entry 051 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00330000
+ (OFFSET, MASK, VALUE) (0XFF9810CC, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_051_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_013_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_013_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_013_PARITY_SHIFT
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_013_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF
- /*Register : APERPERM_014 @ 0XFF981038</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_014_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_014_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_014_PARITY 0x0
-
- Entry 014 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x000E0000
- (OFFSET, MASK, VALUE) (0XFF981038, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_014_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_014_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_014_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_014_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_014_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_014_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_014_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF
- /*Register : APERPERM_015 @ 0XFF98103C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_015_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_015_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_015_PARITY 0x0
-
- Entry 015 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x000F0000
- (OFFSET, MASK, VALUE) (0XFF98103C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_015_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_015_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_015_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_015_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_015_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_015_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_015_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF
- /*Register : APERPERM_016 @ 0XFF981040</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_016_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_016_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_016_PARITY 0x0
-
- Entry 016 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00100000
- (OFFSET, MASK, VALUE) (0XFF981040, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_016_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_016_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_016_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_016_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_016_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_016_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_016_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF
- /*Register : APERPERM_017 @ 0XFF981044</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_017_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_017_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_017_PARITY 0x0
-
- Entry 017 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00110000
- (OFFSET, MASK, VALUE) (0XFF981044, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_017_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_017_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_017_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_017_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_017_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_017_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_017_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF
- /*Register : APERPERM_018 @ 0XFF981048</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_018_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_018_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_018_PARITY 0x0
-
- Entry 018 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00120000
- (OFFSET, MASK, VALUE) (0XFF981048, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_018_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_018_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_018_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_018_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_018_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_018_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_018_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF
- /*Register : APERPERM_019 @ 0XFF98104C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_019_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_019_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_019_PARITY 0x0
-
- Entry 019 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00130000
- (OFFSET, MASK, VALUE) (0XFF98104C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_019_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_019_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_019_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_019_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_019_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_019_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_019_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF
- /*Register : APERPERM_020 @ 0XFF981050</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_020_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_020_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_020_PARITY 0x0
-
- Entry 020 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00140000
- (OFFSET, MASK, VALUE) (0XFF981050, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_020_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_020_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_020_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_020_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_020_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_020_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_020_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF
- /*Register : APERPERM_021 @ 0XFF981054</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_021_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_021_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_021_PARITY 0x0
-
- Entry 021 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00150000
- (OFFSET, MASK, VALUE) (0XFF981054, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_021_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_021_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_021_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_021_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_021_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_021_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_021_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF
- /*Register : APERPERM_022 @ 0XFF981058</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_022_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_022_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_022_PARITY 0x0
-
- Entry 022 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00160000
- (OFFSET, MASK, VALUE) (0XFF981058, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_022_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_022_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_022_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_022_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_022_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_022_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_022_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF
- /*Register : APERPERM_023 @ 0XFF98105C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_023_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_023_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_023_PARITY 0x0
-
- Entry 023 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00170000
- (OFFSET, MASK, VALUE) (0XFF98105C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_023_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_023_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_023_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_023_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_023_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_023_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_023_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_024 @ 0XFF981060</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_024_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_024_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_024_PARITY 0x0
-
- Entry 024 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00180000
- (OFFSET, MASK, VALUE) (0XFF981060, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_024_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_024_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_024_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_024_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_024_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_024_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_024_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_025 @ 0XFF981064</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_025_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_025_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_025_PARITY 0x0
-
- Entry 025 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00190000
- (OFFSET, MASK, VALUE) (0XFF981064, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_025_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_025_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_025_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_025_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_025_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_025_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_025_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_026 @ 0XFF981068</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_026_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_026_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_026_PARITY 0x0
-
- Entry 026 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x001A0000
- (OFFSET, MASK, VALUE) (0XFF981068, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_026_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_026_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_026_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_026_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_026_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_026_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_026_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_027 @ 0XFF98106C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_027_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_027_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_027_PARITY 0x0
-
- Entry 027 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x001B0000
- (OFFSET, MASK, VALUE) (0XFF98106C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_027_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_027_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_027_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_027_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_027_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_027_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_027_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_028 @ 0XFF981070</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_028_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_028_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_028_PARITY 0x0
-
- Entry 028 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x001C0000
- (OFFSET, MASK, VALUE) (0XFF981070, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_028_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_028_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_028_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_028_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_028_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_028_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_028_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_029 @ 0XFF981074</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_029_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_029_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_029_PARITY 0x0
-
- Entry 029 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x001D0000
- (OFFSET, MASK, VALUE) (0XFF981074, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_029_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_029_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_029_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_029_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_029_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_029_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_029_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_030 @ 0XFF981078</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_030_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_030_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_030_PARITY 0x0
-
- Entry 030 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x001E0000
- (OFFSET, MASK, VALUE) (0XFF981078, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_030_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_030_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_030_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_030_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_030_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_030_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_030_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_031 @ 0XFF98107C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_031_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_031_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_031_PARITY 0x0
-
- Entry 031 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x001F0000
- (OFFSET, MASK, VALUE) (0XFF98107C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_031_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_031_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_031_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_031_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_031_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_031_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_031_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_032 @ 0XFF981080</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_032_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_032_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_032_PARITY 0x0
-
- Entry 032 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00200000
- (OFFSET, MASK, VALUE) (0XFF981080, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_032_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_032_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_032_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_032_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_032_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_032_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_032_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_033 @ 0XFF981084</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_033_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_033_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_033_PARITY 0x0
-
- Entry 033 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00210000
- (OFFSET, MASK, VALUE) (0XFF981084, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_033_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_033_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_033_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_033_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_033_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_033_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_033_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_034 @ 0XFF981088</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_034_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_034_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_034_PARITY 0x0
-
- Entry 034 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00220000
- (OFFSET, MASK, VALUE) (0XFF981088, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_034_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_034_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_034_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_034_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_034_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_034_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_034_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
- /*Register : APERPERM_035 @ 0XFF98108C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_035_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_035_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_035_PARITY 0x0
-
- Entry 035 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00230000
- (OFFSET, MASK, VALUE) (0XFF98108C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_035_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_035_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_035_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_035_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_035_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_035_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_035_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF24FFFF
- /*Register : APERPERM_036 @ 0XFF981090</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_036_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_036_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_036_PARITY 0x0
-
- Entry 036 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00240000
- (OFFSET, MASK, VALUE) (0XFF981090, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_036_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_036_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_036_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_036_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_036_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_036_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_036_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF
- /*Register : APERPERM_037 @ 0XFF981094</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_037_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_037_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_037_PARITY 0x0
-
- Entry 037 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00250000
- (OFFSET, MASK, VALUE) (0XFF981094, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_037_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_037_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_037_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_037_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_037_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_037_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_037_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFFF
- /*Register : APERPERM_038 @ 0XFF981098</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_038_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_038_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_038_PARITY 0x0
-
- Entry 038 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00260000
- (OFFSET, MASK, VALUE) (0XFF981098, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_038_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_038_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_038_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_038_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_038_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_038_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_038_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
- /*Register : APERPERM_039 @ 0XFF98109C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_039_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_039_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_039_PARITY 0x0
-
- Entry 039 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00270000
- (OFFSET, MASK, VALUE) (0XFF98109C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_039_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_039_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_039_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_039_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_039_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_039_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_039_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
- /*Register : APERPERM_040 @ 0XFF9810A0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_040_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_040_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_040_PARITY 0x0
-
- Entry 040 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00280000
- (OFFSET, MASK, VALUE) (0XFF9810A0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_040_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_040_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_040_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_040_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_040_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_040_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_040_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
- /*Register : APERPERM_041 @ 0XFF9810A4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_041_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_041_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_041_PARITY 0x0
-
- Entry 041 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00290000
- (OFFSET, MASK, VALUE) (0XFF9810A4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_041_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_041_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_041_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_041_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_041_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_041_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_041_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
- /*Register : APERPERM_042 @ 0XFF9810A8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_042_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_042_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_042_PARITY 0x0
-
- Entry 042 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x002A0000
- (OFFSET, MASK, VALUE) (0XFF9810A8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_042_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_042_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_042_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_042_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_042_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_042_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_042_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
- /*Register : APERPERM_043 @ 0XFF9810AC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_043_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_043_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_043_PARITY 0x0
-
- Entry 043 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x002B0000
- (OFFSET, MASK, VALUE) (0XFF9810AC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_043_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_043_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_043_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_043_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_043_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_043_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_043_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
- /*Register : APERPERM_044 @ 0XFF9810B0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_044_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_044_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_044_PARITY 0x0
-
- Entry 044 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x002C0000
- (OFFSET, MASK, VALUE) (0XFF9810B0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_044_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_044_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_044_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_044_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_044_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_044_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_044_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
- /*Register : APERPERM_045 @ 0XFF9810B4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_045_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_045_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_045_PARITY 0x0
-
- Entry 045 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x002D0000
- (OFFSET, MASK, VALUE) (0XFF9810B4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_045_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_045_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_045_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_045_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_045_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_045_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_045_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
- /*Register : APERPERM_046 @ 0XFF9810B8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_046_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_046_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_046_PARITY 0x0
-
- Entry 046 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x002E0000
- (OFFSET, MASK, VALUE) (0XFF9810B8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_046_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_046_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_046_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_046_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_046_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_046_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_046_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
- /*Register : APERPERM_047 @ 0XFF9810BC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_047_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_047_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_047_PARITY 0x0
-
- Entry 047 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x002F0000
- (OFFSET, MASK, VALUE) (0XFF9810BC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_047_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_047_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_047_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_047_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_047_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_047_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_047_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_048 @ 0XFF9810C0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_048_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_048_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_048_PARITY 0x0
-
- Entry 048 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00300000
- (OFFSET, MASK, VALUE) (0XFF9810C0, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_048_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_048_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_049 @ 0XFF9810C4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_049_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_049_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_049_PARITY 0x0
-
- Entry 049 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00310000
- (OFFSET, MASK, VALUE) (0XFF9810C4, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_049_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_049_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_050 @ 0XFF9810C8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_050_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_050_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_050_PARITY 0x0
-
- Entry 050 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00320000
- (OFFSET, MASK, VALUE) (0XFF9810C8, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_050_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_050_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_051 @ 0XFF9810CC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_051_PERMISSION 0x20
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_051_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_051_PARITY 0x0
-
- Entry 051 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00330000
- (OFFSET, MASK, VALUE) (0XFF9810CC, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_051_PARITY_MASK | 0 );
-
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_051_OFFSET ,0xF80FFFFFU ,0x08000020U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_052 @ 0XFF9810D0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_052_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_052_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_052_PARITY 0x0
-
- Entry 052 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00340000
- (OFFSET, MASK, VALUE) (0XFF9810D0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_052_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_052_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_052_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_052_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_052_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_052_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_052_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_053 @ 0XFF9810D4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_053_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_053_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_053_PARITY 0x0
-
- Entry 053 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00350000
- (OFFSET, MASK, VALUE) (0XFF9810D4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_053_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_053_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_053_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_053_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_053_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_053_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_053_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_054 @ 0XFF9810D8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_054_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_054_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_054_PARITY 0x0
-
- Entry 054 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00360000
- (OFFSET, MASK, VALUE) (0XFF9810D8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_054_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_054_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_054_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_054_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_054_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_054_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_054_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_055 @ 0XFF9810DC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_055_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_055_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_055_PARITY 0x0
-
- Entry 055 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00370000
- (OFFSET, MASK, VALUE) (0XFF9810DC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_055_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_055_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_055_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_055_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_055_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_055_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_055_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
- /*Register : APERPERM_056 @ 0XFF9810E0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_056_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_056_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_056_PARITY 0x0
-
- Entry 056 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00380000
- (OFFSET, MASK, VALUE) (0XFF9810E0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_056_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_056_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_056_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_056_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_056_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_056_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_056_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
- /*Register : APERPERM_057 @ 0XFF9810E4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_057_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_057_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_057_PARITY 0x0
-
- Entry 057 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00390000
- (OFFSET, MASK, VALUE) (0XFF9810E4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_057_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_057_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_057_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_057_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_057_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_057_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_057_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
- /*Register : APERPERM_058 @ 0XFF9810E8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_058_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_058_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_058_PARITY 0x0
-
- Entry 058 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x003A0000
- (OFFSET, MASK, VALUE) (0XFF9810E8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_058_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_058_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_058_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_058_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_058_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_058_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_058_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
- /*Register : APERPERM_059 @ 0XFF9810EC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_059_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_059_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_059_PARITY 0x0
-
- Entry 059 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x003B0000
- (OFFSET, MASK, VALUE) (0XFF9810EC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_059_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_059_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_059_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_059_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_059_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_059_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_059_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
- /*Register : APERPERM_060 @ 0XFF9810F0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_060_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_060_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_060_PARITY 0x0
-
- Entry 060 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x003C0000
- (OFFSET, MASK, VALUE) (0XFF9810F0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_060_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_060_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_060_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_060_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_060_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_060_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_060_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
- /*Register : APERPERM_061 @ 0XFF9810F4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_061_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_061_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_061_PARITY 0x0
-
- Entry 061 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x003D0000
- (OFFSET, MASK, VALUE) (0XFF9810F4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_061_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_061_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_061_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_061_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_061_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_061_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_061_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
- /*Register : APERPERM_062 @ 0XFF9810F8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_062_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_062_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_062_PARITY 0x0
-
- Entry 062 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x003E0000
- (OFFSET, MASK, VALUE) (0XFF9810F8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_062_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_062_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_062_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_062_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_062_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_062_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_062_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
- /*Register : APERPERM_063 @ 0XFF9810FC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_063_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_063_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_063_PARITY 0x0
-
- Entry 063 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x003F0000
- (OFFSET, MASK, VALUE) (0XFF9810FC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_063_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_063_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_063_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_063_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_063_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_063_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_063_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40FFFF
- /*Register : APERPERM_064 @ 0XFF981100</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_064_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_064_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_064_PARITY 0x0
-
- Entry 064 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00400000
- (OFFSET, MASK, VALUE) (0XFF981100, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_064_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_064_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_064_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_064_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_064_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_064_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_064_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_065 @ 0XFF981104</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_065_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_065_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_065_PARITY 0x0
-
- Entry 065 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00410000
- (OFFSET, MASK, VALUE) (0XFF981104, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_065_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_065_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_065_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_065_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_065_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_065_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_065_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_066 @ 0XFF981108</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_066_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_066_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_066_PARITY 0x0
-
- Entry 066 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00420000
- (OFFSET, MASK, VALUE) (0XFF981108, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_066_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_066_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_066_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_066_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_066_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_066_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_066_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_067 @ 0XFF98110C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_067_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_067_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_067_PARITY 0x0
-
- Entry 067 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00430000
- (OFFSET, MASK, VALUE) (0XFF98110C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_067_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_067_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_067_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_067_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_067_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_067_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_067_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_068 @ 0XFF981110</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_068_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_068_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_068_PARITY 0x0
-
- Entry 068 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00440000
- (OFFSET, MASK, VALUE) (0XFF981110, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_068_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_068_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_068_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_068_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_068_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_068_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_068_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_069 @ 0XFF981114</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_069_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_069_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_069_PARITY 0x0
-
- Entry 069 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00450000
- (OFFSET, MASK, VALUE) (0XFF981114, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_069_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_069_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_069_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_069_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_069_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_069_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_069_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_070 @ 0XFF981118</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_070_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_070_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_070_PARITY 0x0
-
- Entry 070 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00460000
- (OFFSET, MASK, VALUE) (0XFF981118, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_070_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_070_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_070_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_070_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_070_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_070_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_070_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_071 @ 0XFF98111C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_071_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_071_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_071_PARITY 0x0
-
- Entry 071 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00470000
- (OFFSET, MASK, VALUE) (0XFF98111C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_071_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_071_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_071_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_071_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_071_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_071_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_071_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_072 @ 0XFF981120</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_072_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_072_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_072_PARITY 0x0
-
- Entry 072 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00480000
- (OFFSET, MASK, VALUE) (0XFF981120, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_072_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_072_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_072_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_072_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_072_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_072_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_072_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_073 @ 0XFF981124</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_073_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_073_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_073_PARITY 0x0
-
- Entry 073 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00490000
- (OFFSET, MASK, VALUE) (0XFF981124, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_073_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_073_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_073_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_073_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_073_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_073_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_073_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
- /*Register : APERPERM_074 @ 0XFF981128</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_074_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_074_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_074_PARITY 0x0
-
- Entry 074 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x004A0000
- (OFFSET, MASK, VALUE) (0XFF981128, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_074_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_074_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_074_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_074_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_074_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_074_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_074_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
- /*Register : APERPERM_075 @ 0XFF98112C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_075_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_075_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_075_PARITY 0x0
-
- Entry 075 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x004B0000
- (OFFSET, MASK, VALUE) (0XFF98112C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_075_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_075_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_075_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_075_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_075_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_075_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_075_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
- /*Register : APERPERM_076 @ 0XFF981130</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_076_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_076_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_076_PARITY 0x0
-
- Entry 076 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x004C0000
- (OFFSET, MASK, VALUE) (0XFF981130, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_076_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_076_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_076_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_076_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_076_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_076_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_076_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
- /*Register : APERPERM_077 @ 0XFF981134</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_077_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_077_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_077_PARITY 0x0
-
- Entry 077 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x004D0000
- (OFFSET, MASK, VALUE) (0XFF981134, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_077_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_077_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_077_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_077_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_077_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_077_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_077_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_078 @ 0XFF981138</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_078_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_078_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_078_PARITY 0x0
-
- Entry 078 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x004E0000
- (OFFSET, MASK, VALUE) (0XFF981138, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_078_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_078_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_078_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_078_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_078_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_078_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_078_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_079 @ 0XFF98113C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_079_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_079_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_079_PARITY 0x0
-
- Entry 079 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x004F0000
- (OFFSET, MASK, VALUE) (0XFF98113C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_079_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_079_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_079_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_079_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_079_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_079_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_079_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_080 @ 0XFF981140</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_080_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_080_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_080_PARITY 0x0
-
- Entry 080 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00500000
- (OFFSET, MASK, VALUE) (0XFF981140, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_080_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_080_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_080_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_080_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_080_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_080_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_080_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_081 @ 0XFF981144</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_081_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_081_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_081_PARITY 0x0
-
- Entry 081 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00510000
- (OFFSET, MASK, VALUE) (0XFF981144, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_081_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_081_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_081_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_081_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_081_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_081_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_081_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_082 @ 0XFF981148</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_082_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_082_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_082_PARITY 0x0
-
- Entry 082 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00520000
- (OFFSET, MASK, VALUE) (0XFF981148, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_082_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_082_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_082_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_082_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_082_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_082_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_082_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_083 @ 0XFF98114C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_083_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_083_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_083_PARITY 0x0
-
- Entry 083 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00530000
- (OFFSET, MASK, VALUE) (0XFF98114C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_083_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_083_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_083_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_083_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_083_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_083_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_083_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_084 @ 0XFF981150</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_084_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_084_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_084_PARITY 0x0
-
- Entry 084 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00540000
- (OFFSET, MASK, VALUE) (0XFF981150, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_084_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_084_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_084_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_084_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_084_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_084_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_084_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_085 @ 0XFF981154</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_085_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_085_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_085_PARITY 0x0
-
- Entry 085 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00550000
- (OFFSET, MASK, VALUE) (0XFF981154, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_085_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_085_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_085_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_085_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_085_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_085_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_085_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_086 @ 0XFF981158</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_086_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_086_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_086_PARITY 0x0
-
- Entry 086 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00560000
- (OFFSET, MASK, VALUE) (0XFF981158, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_086_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_086_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_086_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_086_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_086_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_086_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_086_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_087 @ 0XFF98115C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_087_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_087_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_087_PARITY 0x0
-
- Entry 087 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00570000
- (OFFSET, MASK, VALUE) (0XFF98115C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_087_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_087_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_087_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_087_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_087_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_087_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_087_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_088 @ 0XFF981160</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_088_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_088_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_088_PARITY 0x0
-
- Entry 088 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00580000
- (OFFSET, MASK, VALUE) (0XFF981160, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_088_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_088_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_088_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_088_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_088_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_088_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_088_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_089 @ 0XFF981164</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_089_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_089_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_089_PARITY 0x0
-
- Entry 089 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00590000
- (OFFSET, MASK, VALUE) (0XFF981164, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_089_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_089_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_089_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_089_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_089_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_089_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_089_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_090 @ 0XFF981168</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_090_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_090_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_090_PARITY 0x0
-
- Entry 090 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x005A0000
- (OFFSET, MASK, VALUE) (0XFF981168, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_090_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_090_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_090_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_090_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_090_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_090_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_090_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_091 @ 0XFF98116C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_091_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_091_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_091_PARITY 0x0
-
- Entry 091 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x005B0000
- (OFFSET, MASK, VALUE) (0XFF98116C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_091_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_091_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_091_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_091_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_091_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_091_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_091_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_092 @ 0XFF981170</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_092_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_092_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_092_PARITY 0x0
-
- Entry 092 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x005C0000
- (OFFSET, MASK, VALUE) (0XFF981170, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_092_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_092_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_092_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_092_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_092_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_092_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_092_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
- /*Register : APERPERM_093 @ 0XFF981174</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_093_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_093_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_093_PARITY 0x0
-
- Entry 093 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x005D0000
- (OFFSET, MASK, VALUE) (0XFF981174, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_093_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_093_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_093_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_093_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_093_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_093_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_093_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_094 @ 0XFF981178</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_094_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_094_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_094_PARITY 0x0
-
- Entry 094 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x005E0000
- (OFFSET, MASK, VALUE) (0XFF981178, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_094_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_094_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_094_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_094_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_094_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_094_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_094_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_095 @ 0XFF98117C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_095_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_095_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_095_PARITY 0x0
-
- Entry 095 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x005F0000
- (OFFSET, MASK, VALUE) (0XFF98117C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_095_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_095_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_095_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_095_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_095_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_095_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_095_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_096 @ 0XFF981180</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_096_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_096_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_096_PARITY 0x0
-
- Entry 096 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00600000
- (OFFSET, MASK, VALUE) (0XFF981180, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_096_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_096_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_096_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_096_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_096_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_096_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_096_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_097 @ 0XFF981184</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_097_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_097_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_097_PARITY 0x0
-
- Entry 097 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00610000
- (OFFSET, MASK, VALUE) (0XFF981184, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_097_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_097_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_097_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_097_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_097_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_097_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_097_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_098 @ 0XFF981188</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_098_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_098_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_098_PARITY 0x0
-
- Entry 098 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00620000
- (OFFSET, MASK, VALUE) (0XFF981188, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_098_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_098_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_098_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_098_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_098_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_098_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_098_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_099 @ 0XFF98118C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_099_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_099_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_099_PARITY 0x0
-
- Entry 099 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00630000
- (OFFSET, MASK, VALUE) (0XFF98118C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_099_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_099_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_099_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_099_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_099_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_099_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_099_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_100 @ 0XFF981190</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_100_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_100_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_100_PARITY 0x0
-
- Entry 100 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00640000
- (OFFSET, MASK, VALUE) (0XFF981190, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_100_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_100_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_100_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_100_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_100_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_100_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_100_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_101 @ 0XFF981194</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_101_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_101_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_101_PARITY 0x0
-
- Entry 101 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00650000
- (OFFSET, MASK, VALUE) (0XFF981194, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_101_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_101_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_101_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_101_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_101_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_101_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_101_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_102 @ 0XFF981198</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_102_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_102_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_102_PARITY 0x0
-
- Entry 102 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00660000
- (OFFSET, MASK, VALUE) (0XFF981198, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_102_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_102_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_102_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_102_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_102_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_102_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_102_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_103 @ 0XFF98119C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_103_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_103_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_103_PARITY 0x0
-
- Entry 103 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00670000
- (OFFSET, MASK, VALUE) (0XFF98119C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_103_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_103_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_103_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_103_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_103_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_103_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_103_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_104 @ 0XFF9811A0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_104_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_104_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_104_PARITY 0x0
-
- Entry 104 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00680000
- (OFFSET, MASK, VALUE) (0XFF9811A0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_104_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_104_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_104_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_104_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_104_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_104_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_104_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_105 @ 0XFF9811A4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_105_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_105_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_105_PARITY 0x0
-
- Entry 105 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00690000
- (OFFSET, MASK, VALUE) (0XFF9811A4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_105_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_105_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_105_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_105_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_105_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_105_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_105_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_106 @ 0XFF9811A8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_106_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_106_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_106_PARITY 0x0
-
- Entry 106 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x006A0000
- (OFFSET, MASK, VALUE) (0XFF9811A8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_106_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_106_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_106_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_106_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_106_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_106_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_106_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_107 @ 0XFF9811AC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_107_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_107_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_107_PARITY 0x0
-
- Entry 107 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x006B0000
- (OFFSET, MASK, VALUE) (0XFF9811AC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_107_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_107_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_107_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_107_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_107_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_107_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_107_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_108 @ 0XFF9811B0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_108_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_108_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_108_PARITY 0x0
-
- Entry 108 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x006C0000
- (OFFSET, MASK, VALUE) (0XFF9811B0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_108_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_108_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_108_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_108_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_108_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_108_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_108_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_109 @ 0XFF9811B4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_109_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_109_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_109_PARITY 0x0
-
- Entry 109 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x006D0000
- (OFFSET, MASK, VALUE) (0XFF9811B4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_109_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_109_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_109_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_109_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_109_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_109_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_109_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_110 @ 0XFF9811B8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_110_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_110_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_110_PARITY 0x0
-
- Entry 110 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x006E0000
- (OFFSET, MASK, VALUE) (0XFF9811B8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_110_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_110_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_110_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_110_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_110_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_110_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_110_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_111 @ 0XFF9811BC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_111_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_111_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_111_PARITY 0x0
-
- Entry 111 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x006F0000
- (OFFSET, MASK, VALUE) (0XFF9811BC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_111_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_111_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_111_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_111_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_111_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_111_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_111_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_112 @ 0XFF9811C0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_112_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_112_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_112_PARITY 0x0
-
- Entry 112 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00700000
- (OFFSET, MASK, VALUE) (0XFF9811C0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_112_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_112_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_112_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_112_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_112_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_112_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_112_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_113 @ 0XFF9811C4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_113_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_113_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_113_PARITY 0x0
-
- Entry 113 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00710000
- (OFFSET, MASK, VALUE) (0XFF9811C4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_113_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_113_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_113_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_113_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_113_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_113_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_113_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_114 @ 0XFF9811C8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_114_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_114_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_114_PARITY 0x0
-
- Entry 114 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00720000
- (OFFSET, MASK, VALUE) (0XFF9811C8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_114_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_114_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_114_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_114_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_114_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_114_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_114_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_115 @ 0XFF9811CC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_115_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_115_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_115_PARITY 0x0
-
- Entry 115 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00730000
- (OFFSET, MASK, VALUE) (0XFF9811CC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_115_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_115_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_115_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_115_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_115_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_115_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_115_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_116 @ 0XFF9811D0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_116_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_116_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_116_PARITY 0x0
-
- Entry 116 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00740000
- (OFFSET, MASK, VALUE) (0XFF9811D0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_116_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_116_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_116_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_116_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_116_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_116_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_116_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_117 @ 0XFF9811D4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_117_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_117_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_117_PARITY 0x0
-
- Entry 117 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00750000
- (OFFSET, MASK, VALUE) (0XFF9811D4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_117_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_117_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_117_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_117_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_117_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_117_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_117_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_118 @ 0XFF9811D8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_118_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_118_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_118_PARITY 0x0
-
- Entry 118 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00760000
- (OFFSET, MASK, VALUE) (0XFF9811D8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_118_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_118_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_118_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_118_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_118_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_118_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_118_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_119 @ 0XFF9811DC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_119_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_119_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_119_PARITY 0x0
-
- Entry 119 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00770000
- (OFFSET, MASK, VALUE) (0XFF9811DC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_119_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_119_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_119_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_119_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_119_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_119_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_119_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_120 @ 0XFF9811E0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_120_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_120_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_120_PARITY 0x0
-
- Entry 120 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00780000
- (OFFSET, MASK, VALUE) (0XFF9811E0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_120_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_120_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_120_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_120_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_120_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_120_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_120_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_121 @ 0XFF9811E4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_121_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_121_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_121_PARITY 0x0
-
- Entry 121 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00790000
- (OFFSET, MASK, VALUE) (0XFF9811E4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_121_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_121_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_121_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_121_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_121_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_121_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_121_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_122 @ 0XFF9811E8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_122_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_122_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_122_PARITY 0x0
-
- Entry 122 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x007A0000
- (OFFSET, MASK, VALUE) (0XFF9811E8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_122_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_122_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_122_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_122_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_122_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_122_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_122_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_123 @ 0XFF9811EC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_123_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_123_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_123_PARITY 0x0
-
- Entry 123 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x007B0000
- (OFFSET, MASK, VALUE) (0XFF9811EC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_123_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_123_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_123_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_123_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_123_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_123_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_123_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_124 @ 0XFF9811F0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_124_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_124_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_124_PARITY 0x0
-
- Entry 124 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x007C0000
- (OFFSET, MASK, VALUE) (0XFF9811F0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_124_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_124_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_124_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_124_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_124_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_124_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_124_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_125 @ 0XFF9811F4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_125_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_125_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_125_PARITY 0x0
-
- Entry 125 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x007D0000
- (OFFSET, MASK, VALUE) (0XFF9811F4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_125_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_125_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_125_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_125_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_125_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_125_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_125_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_126 @ 0XFF9811F8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_126_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_126_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_126_PARITY 0x0
-
- Entry 126 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x007E0000
- (OFFSET, MASK, VALUE) (0XFF9811F8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_126_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_126_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_126_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_126_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_126_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_126_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_126_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_127 @ 0XFF9811FC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_127_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_127_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_127_PARITY 0x0
-
- Entry 127 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x007F0000
- (OFFSET, MASK, VALUE) (0XFF9811FC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_127_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_127_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_127_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_127_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_127_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_127_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_127_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_128 @ 0XFF981200</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_128_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_128_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_128_PARITY 0x0
-
- Entry 128 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00800000
- (OFFSET, MASK, VALUE) (0XFF981200, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_128_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_128_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_128_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_128_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_128_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_128_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_128_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_129 @ 0XFF981204</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_129_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_129_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_129_PARITY 0x0
-
- Entry 129 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00810000
- (OFFSET, MASK, VALUE) (0XFF981204, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_129_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_129_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_129_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_129_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_129_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_129_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_129_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_130 @ 0XFF981208</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_130_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_130_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_130_PARITY 0x0
-
- Entry 130 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00820000
- (OFFSET, MASK, VALUE) (0XFF981208, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_130_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_130_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_130_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_130_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_130_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_130_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_130_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_131 @ 0XFF98120C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_131_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_131_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_131_PARITY 0x0
-
- Entry 131 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00830000
- (OFFSET, MASK, VALUE) (0XFF98120C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_131_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_131_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_131_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_131_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_131_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_131_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_131_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_132 @ 0XFF981210</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_132_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_132_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_132_PARITY 0x0
-
- Entry 132 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00840000
- (OFFSET, MASK, VALUE) (0XFF981210, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_132_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_132_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_132_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_132_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_132_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_132_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_132_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
- /*Register : APERPERM_133 @ 0XFF981214</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_133_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_133_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_133_PARITY 0x0
-
- Entry 133 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00850000
- (OFFSET, MASK, VALUE) (0XFF981214, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_133_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_133_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_133_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_133_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_133_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_133_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_133_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_134 @ 0XFF981218</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_134_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_134_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_134_PARITY 0x0
-
- Entry 134 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00860000
- (OFFSET, MASK, VALUE) (0XFF981218, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_134_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_134_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_134_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_134_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_134_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_134_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_134_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_135 @ 0XFF98121C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_135_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_135_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_135_PARITY 0x0
-
- Entry 135 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00870000
- (OFFSET, MASK, VALUE) (0XFF98121C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_135_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_135_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_135_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_135_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_135_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_135_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_135_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_136 @ 0XFF981220</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_136_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_136_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_136_PARITY 0x0
-
- Entry 136 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00880000
- (OFFSET, MASK, VALUE) (0XFF981220, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_136_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_136_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_136_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_136_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_136_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_136_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_136_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_137 @ 0XFF981224</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_137_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_137_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_137_PARITY 0x0
-
- Entry 137 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00890000
- (OFFSET, MASK, VALUE) (0XFF981224, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_137_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_137_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_137_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_137_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_137_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_137_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_137_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_138 @ 0XFF981228</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_138_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_138_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_138_PARITY 0x0
-
- Entry 138 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x008A0000
- (OFFSET, MASK, VALUE) (0XFF981228, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_138_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_138_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_138_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_138_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_138_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_138_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_138_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_139 @ 0XFF98122C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_139_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_139_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_139_PARITY 0x0
-
- Entry 139 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x008B0000
- (OFFSET, MASK, VALUE) (0XFF98122C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_139_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_139_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_139_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_139_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_139_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_139_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_139_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_140 @ 0XFF981230</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_140_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_140_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_140_PARITY 0x0
-
- Entry 140 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x008C0000
- (OFFSET, MASK, VALUE) (0XFF981230, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_140_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_140_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_140_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_140_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_140_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_140_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_140_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_141 @ 0XFF981234</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_141_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_141_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_141_PARITY 0x0
-
- Entry 141 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x008D0000
- (OFFSET, MASK, VALUE) (0XFF981234, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_141_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_141_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_141_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_141_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_141_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_141_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_141_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_142 @ 0XFF981238</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_142_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_142_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_142_PARITY 0x0
-
- Entry 142 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x008E0000
- (OFFSET, MASK, VALUE) (0XFF981238, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_142_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_142_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_142_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_142_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_142_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_142_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_142_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_143 @ 0XFF98123C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_143_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_143_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_143_PARITY 0x0
-
- Entry 143 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x008F0000
- (OFFSET, MASK, VALUE) (0XFF98123C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_143_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_143_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_143_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_143_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_143_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_143_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_143_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_144 @ 0XFF981240</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_144_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_144_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_144_PARITY 0x0
-
- Entry 144 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00900000
- (OFFSET, MASK, VALUE) (0XFF981240, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_144_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_144_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_144_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_144_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_144_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_144_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_144_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_145 @ 0XFF981244</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_145_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_145_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_145_PARITY 0x0
-
- Entry 145 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00910000
- (OFFSET, MASK, VALUE) (0XFF981244, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_145_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_145_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_145_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_145_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_145_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_145_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_145_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_146 @ 0XFF981248</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_146_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_146_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_146_PARITY 0x0
-
- Entry 146 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00920000
- (OFFSET, MASK, VALUE) (0XFF981248, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_146_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_146_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_146_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_146_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_146_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_146_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_146_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_147 @ 0XFF98124C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_147_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_147_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_147_PARITY 0x0
-
- Entry 147 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00930000
- (OFFSET, MASK, VALUE) (0XFF98124C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_147_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_147_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_147_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_147_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_147_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_147_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_147_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_148 @ 0XFF981250</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_148_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_148_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_148_PARITY 0x0
-
- Entry 148 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00940000
- (OFFSET, MASK, VALUE) (0XFF981250, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_148_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_148_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_148_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_148_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_148_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_148_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_148_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
- /*Register : APERPERM_149 @ 0XFF981254</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_149_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_149_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_149_PARITY 0x0
-
- Entry 149 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00950000
- (OFFSET, MASK, VALUE) (0XFF981254, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_149_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_149_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_149_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_149_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_149_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_149_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_149_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF
- /*Register : APERPERM_150 @ 0XFF981258</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_150_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_150_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_150_PARITY 0x0
-
- Entry 150 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00960000
- (OFFSET, MASK, VALUE) (0XFF981258, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_150_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_150_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_150_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_150_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_150_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_150_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_150_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97FFFF
- /*Register : APERPERM_151 @ 0XFF98125C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_151_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_151_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_151_PARITY 0x0
-
- Entry 151 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00970000
- (OFFSET, MASK, VALUE) (0XFF98125C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_151_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_151_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_151_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_151_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_151_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_151_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_151_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
- /*Register : APERPERM_152 @ 0XFF981260</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_152_PERMISSION 0x0
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_152_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_152_PARITY 0x0
-
- Entry 152 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00980000
- (OFFSET, MASK, VALUE) (0XFF981260, 0xF80FFFFFU ,0x08000000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_152_PARITY_MASK | 0 );
-
- RegVal = ((0x00000000U << LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_152_OFFSET ,0xF80FFFFFU ,0x08000000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
- /*Register : APERPERM_153 @ 0XFF981264</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_153_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_153_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_153_PARITY 0x0
-
- Entry 153 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00990000
- (OFFSET, MASK, VALUE) (0XFF981264, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_153_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_153_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_153_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_153_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_153_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_153_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_153_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF
- /*Register : APERPERM_154 @ 0XFF981268</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_154_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_154_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_154_PARITY 0x0
-
- Entry 154 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x009A0000
- (OFFSET, MASK, VALUE) (0XFF981268, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_154_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_154_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_154_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_154_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_154_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_154_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_154_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF
- /*Register : APERPERM_155 @ 0XFF98126C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_155_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_155_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_155_PARITY 0x0
-
- Entry 155 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x009B0000
- (OFFSET, MASK, VALUE) (0XFF98126C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_155_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_155_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_155_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_155_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_155_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_155_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_155_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9CFFFF
- /*Register : APERPERM_156 @ 0XFF981270</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_156_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_156_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_156_PARITY 0x0
-
- Entry 156 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x009C0000
- (OFFSET, MASK, VALUE) (0XFF981270, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_156_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_156_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_156_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_156_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_156_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_156_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_156_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF
- /*Register : APERPERM_157 @ 0XFF981274</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_157_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_157_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_157_PARITY 0x0
-
- Entry 157 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x009D0000
- (OFFSET, MASK, VALUE) (0XFF981274, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_157_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_157_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_157_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_157_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_157_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_157_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_157_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF
- /*Register : APERPERM_158 @ 0XFF981278</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_158_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_158_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_158_PARITY 0x0
-
- Entry 158 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x009E0000
- (OFFSET, MASK, VALUE) (0XFF981278, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_158_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_158_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_158_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_158_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_158_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_158_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_158_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FFFFF
- /*Register : APERPERM_159 @ 0XFF98127C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_159_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_159_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_159_PARITY 0x0
-
- Entry 159 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x009F0000
- (OFFSET, MASK, VALUE) (0XFF98127C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_159_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_159_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_159_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_159_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_159_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_159_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_159_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF
- /*Register : APERPERM_160 @ 0XFF981280</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_160_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_160_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_160_PARITY 0x0
-
- Entry 160 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A00000
- (OFFSET, MASK, VALUE) (0XFF981280, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_160_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_160_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_160_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_160_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_160_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_160_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_160_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF
- /*Register : APERPERM_161 @ 0XFF981284</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_161_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_161_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_161_PARITY 0x0
-
- Entry 161 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A10000
- (OFFSET, MASK, VALUE) (0XFF981284, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_161_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_161_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_161_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_161_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_161_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_161_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_161_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2FFFF
- /*Register : APERPERM_162 @ 0XFF981288</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_162_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_162_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_162_PARITY 0x0
-
- Entry 162 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A20000
- (OFFSET, MASK, VALUE) (0XFF981288, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_162_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_162_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_162_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_162_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_162_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_162_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_162_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FFFF
- /*Register : APERPERM_163 @ 0XFF98128C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_163_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_163_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_163_PARITY 0x0
-
- Entry 163 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A30000
- (OFFSET, MASK, VALUE) (0XFF98128C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_163_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_163_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_163_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_163_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_163_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_163_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_163_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4FFFF
- /*Register : APERPERM_164 @ 0XFF981290</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_164_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_164_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_164_PARITY 0x0
-
- Entry 164 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A40000
- (OFFSET, MASK, VALUE) (0XFF981290, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_164_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_164_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_164_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_164_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_164_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_164_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_164_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF
- /*Register : APERPERM_165 @ 0XFF981294</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_165_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_165_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_165_PARITY 0x0
-
- Entry 165 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A50000
- (OFFSET, MASK, VALUE) (0XFF981294, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_165_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_165_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_165_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_165_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_165_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_165_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_165_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF
- /*Register : APERPERM_166 @ 0XFF981298</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_166_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_166_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_166_PARITY 0x0
-
- Entry 166 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A60000
- (OFFSET, MASK, VALUE) (0XFF981298, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_166_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_166_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_166_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_166_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_166_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_166_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_166_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7FFFF
- /*Register : APERPERM_167 @ 0XFF98129C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_167_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_167_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_167_PARITY 0x0
-
- Entry 167 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A70000
- (OFFSET, MASK, VALUE) (0XFF98129C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_167_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_167_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_167_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_167_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_167_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_167_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_167_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF
- /*Register : APERPERM_168 @ 0XFF9812A0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_168_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_168_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_168_PARITY 0x0
-
- Entry 168 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A80000
- (OFFSET, MASK, VALUE) (0XFF9812A0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_168_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_168_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_168_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_168_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_168_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_168_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_168_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF
- /*Register : APERPERM_169 @ 0XFF9812A4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_169_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_169_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_169_PARITY 0x0
-
- Entry 169 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00A90000
- (OFFSET, MASK, VALUE) (0XFF9812A4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_169_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_169_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_169_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_169_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_169_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_169_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_169_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF
- /*Register : APERPERM_170 @ 0XFF9812A8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_170_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_170_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_170_PARITY 0x0
-
- Entry 170 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00AA0000
- (OFFSET, MASK, VALUE) (0XFF9812A8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_170_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_170_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_170_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_170_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_170_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_170_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_170_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF
- /*Register : APERPERM_171 @ 0XFF9812AC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_171_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_171_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_171_PARITY 0x0
-
- Entry 171 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00AB0000
- (OFFSET, MASK, VALUE) (0XFF9812AC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_171_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_171_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_171_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_171_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_171_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_171_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_171_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF
- /*Register : APERPERM_172 @ 0XFF9812B0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_172_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_172_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_172_PARITY 0x0
-
- Entry 172 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00AC0000
- (OFFSET, MASK, VALUE) (0XFF9812B0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_172_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_172_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_172_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_172_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_172_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_172_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_172_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF
- /*Register : APERPERM_173 @ 0XFF9812B4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_173_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_173_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_173_PARITY 0x0
-
- Entry 173 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00AD0000
- (OFFSET, MASK, VALUE) (0XFF9812B4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_173_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_173_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_173_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_173_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_173_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_173_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_173_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF
- /*Register : APERPERM_174 @ 0XFF9812B8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_174_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_174_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_174_PARITY 0x0
-
- Entry 174 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00AE0000
- (OFFSET, MASK, VALUE) (0XFF9812B8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_174_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_174_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_174_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_174_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_174_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_174_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_174_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF
- /*Register : APERPERM_175 @ 0XFF9812BC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_175_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_175_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_175_PARITY 0x0
-
- Entry 175 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00AF0000
- (OFFSET, MASK, VALUE) (0XFF9812BC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_175_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_175_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_175_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_175_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_175_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_175_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_175_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_176 @ 0XFF9812C0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_176_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_176_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_176_PARITY 0x0
-
- Entry 176 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B00000
- (OFFSET, MASK, VALUE) (0XFF9812C0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_176_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_176_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_176_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_176_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_176_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_176_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_176_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_177 @ 0XFF9812C4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_177_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_177_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_177_PARITY 0x0
-
- Entry 177 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B10000
- (OFFSET, MASK, VALUE) (0XFF9812C4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_177_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_177_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_177_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_177_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_177_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_177_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_177_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_178 @ 0XFF9812C8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_178_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_178_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_178_PARITY 0x0
-
- Entry 178 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B20000
- (OFFSET, MASK, VALUE) (0XFF9812C8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_178_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_178_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_178_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_178_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_178_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_178_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_178_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_179 @ 0XFF9812CC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_179_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_179_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_179_PARITY 0x0
-
- Entry 179 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B30000
- (OFFSET, MASK, VALUE) (0XFF9812CC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_179_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_179_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_179_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_179_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_179_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_179_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_179_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_180 @ 0XFF9812D0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_180_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_180_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_180_PARITY 0x0
-
- Entry 180 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B40000
- (OFFSET, MASK, VALUE) (0XFF9812D0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_180_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_180_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_180_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_180_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_180_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_180_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_180_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_181 @ 0XFF9812D4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_181_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_181_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_181_PARITY 0x0
-
- Entry 181 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B50000
- (OFFSET, MASK, VALUE) (0XFF9812D4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_181_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_181_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_181_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_181_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_181_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_181_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_181_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_182 @ 0XFF9812D8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_182_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_182_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_182_PARITY 0x0
-
- Entry 182 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B60000
- (OFFSET, MASK, VALUE) (0XFF9812D8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_182_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_182_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_182_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_182_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_182_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_182_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_182_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_183 @ 0XFF9812DC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_183_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_183_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_183_PARITY 0x0
-
- Entry 183 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B70000
- (OFFSET, MASK, VALUE) (0XFF9812DC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_183_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_183_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_183_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_183_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_183_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_183_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_183_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_184 @ 0XFF9812E0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_184_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_184_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_184_PARITY 0x0
-
- Entry 184 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B80000
- (OFFSET, MASK, VALUE) (0XFF9812E0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_184_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_184_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_184_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_184_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_184_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_184_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_184_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_185 @ 0XFF9812E4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_185_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_185_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_185_PARITY 0x0
-
- Entry 185 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00B90000
- (OFFSET, MASK, VALUE) (0XFF9812E4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_185_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_185_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_185_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_185_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_185_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_185_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_185_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_186 @ 0XFF9812E8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_186_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_186_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_186_PARITY 0x0
-
- Entry 186 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00BA0000
- (OFFSET, MASK, VALUE) (0XFF9812E8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_186_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_186_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_186_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_186_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_186_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_186_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_186_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_187 @ 0XFF9812EC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_187_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_187_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_187_PARITY 0x0
-
- Entry 187 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00BB0000
- (OFFSET, MASK, VALUE) (0XFF9812EC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_187_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_187_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_187_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_187_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_187_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_187_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_187_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_188 @ 0XFF9812F0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_188_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_188_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_188_PARITY 0x0
-
- Entry 188 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00BC0000
- (OFFSET, MASK, VALUE) (0XFF9812F0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_188_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_188_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_188_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_188_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_188_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_188_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_188_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_189 @ 0XFF9812F4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_189_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_189_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_189_PARITY 0x0
-
- Entry 189 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00BD0000
- (OFFSET, MASK, VALUE) (0XFF9812F4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_189_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_189_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_189_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_189_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_189_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_189_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_189_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_190 @ 0XFF9812F8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_190_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_190_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_190_PARITY 0x0
-
- Entry 190 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00BE0000
- (OFFSET, MASK, VALUE) (0XFF9812F8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_190_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_190_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_190_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_190_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_190_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_190_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_190_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
- /*Register : APERPERM_191 @ 0XFF9812FC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_191_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_191_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_191_PARITY 0x0
-
- Entry 191 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00BF0000
- (OFFSET, MASK, VALUE) (0XFF9812FC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_191_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_191_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_191_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_191_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_191_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_191_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_191_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
- /*Register : APERPERM_192 @ 0XFF981300</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_192_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_192_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_192_PARITY 0x0
-
- Entry 192 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C00000
- (OFFSET, MASK, VALUE) (0XFF981300, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_192_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_192_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_192_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_192_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_192_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_192_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_192_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
- /*Register : APERPERM_193 @ 0XFF981304</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_193_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_193_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_193_PARITY 0x0
-
- Entry 193 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C10000
- (OFFSET, MASK, VALUE) (0XFF981304, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_193_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_193_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_193_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_193_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_193_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_193_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_193_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF
- /*Register : APERPERM_194 @ 0XFF981308</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_194_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_194_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_194_PARITY 0x0
-
- Entry 194 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C20000
- (OFFSET, MASK, VALUE) (0XFF981308, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_194_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_194_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_194_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_194_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_194_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_194_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_194_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF
- /*Register : APERPERM_195 @ 0XFF98130C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_195_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_195_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_195_PARITY 0x0
-
- Entry 195 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C30000
- (OFFSET, MASK, VALUE) (0XFF98130C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_195_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_195_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_195_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_195_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_195_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_195_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_195_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
- /*Register : APERPERM_196 @ 0XFF981310</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_196_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_196_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_196_PARITY 0x0
-
- Entry 196 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C40000
- (OFFSET, MASK, VALUE) (0XFF981310, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_196_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_196_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_196_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_196_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_196_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_196_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_196_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
- /*Register : APERPERM_197 @ 0XFF981314</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_197_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_197_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_197_PARITY 0x0
-
- Entry 197 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C50000
- (OFFSET, MASK, VALUE) (0XFF981314, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_197_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_197_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_197_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_197_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_197_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_197_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_197_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF
- /*Register : APERPERM_198 @ 0XFF981318</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_198_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_198_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_198_PARITY 0x0
-
- Entry 198 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C60000
- (OFFSET, MASK, VALUE) (0XFF981318, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_198_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_198_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_198_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_198_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_198_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_198_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_198_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF
- /*Register : APERPERM_199 @ 0XFF98131C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_199_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_199_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_199_PARITY 0x0
-
- Entry 199 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C70000
- (OFFSET, MASK, VALUE) (0XFF98131C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_199_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_199_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_199_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_199_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_199_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_199_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_199_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
- /*Register : APERPERM_200 @ 0XFF981320</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_200_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_200_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_200_PARITY 0x0
-
- Entry 200 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C80000
- (OFFSET, MASK, VALUE) (0XFF981320, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_200_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_200_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_200_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_200_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_200_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_200_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_200_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
- /*Register : APERPERM_201 @ 0XFF981324</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_201_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_201_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_201_PARITY 0x0
-
- Entry 201 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00C90000
- (OFFSET, MASK, VALUE) (0XFF981324, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_201_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_201_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_201_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_201_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_201_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_201_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_201_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF
- /*Register : APERPERM_202 @ 0XFF981328</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_202_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_202_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_202_PARITY 0x0
-
- Entry 202 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00CA0000
- (OFFSET, MASK, VALUE) (0XFF981328, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_202_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_202_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_202_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_202_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_202_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_202_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_202_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF
- /*Register : APERPERM_203 @ 0XFF98132C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_203_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_203_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_203_PARITY 0x0
-
- Entry 203 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00CB0000
- (OFFSET, MASK, VALUE) (0XFF98132C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_203_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_203_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_203_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_203_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_203_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_203_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_203_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF
- /*Register : APERPERM_204 @ 0XFF981330</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_204_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_204_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_204_PARITY 0x0
-
- Entry 204 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00CC0000
- (OFFSET, MASK, VALUE) (0XFF981330, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_204_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_204_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_204_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_204_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_204_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_204_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_204_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF
- /*Register : APERPERM_205 @ 0XFF981334</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_205_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_205_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_205_PARITY 0x0
-
- Entry 205 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00CD0000
- (OFFSET, MASK, VALUE) (0XFF981334, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_205_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_205_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_205_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_205_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_205_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_205_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_205_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF
- /*Register : APERPERM_206 @ 0XFF981338</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_206_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_206_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_206_PARITY 0x0
-
- Entry 206 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00CE0000
- (OFFSET, MASK, VALUE) (0XFF981338, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_206_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_206_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_206_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_206_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_206_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_206_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_206_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF
- /*Register : APERPERM_207 @ 0XFF98133C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_207_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_207_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_207_PARITY 0x0
-
- Entry 207 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00CF0000
- (OFFSET, MASK, VALUE) (0XFF98133C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_207_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_207_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_207_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_207_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_207_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_207_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_207_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
- /*Register : APERPERM_208 @ 0XFF981340</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_208_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_208_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_208_PARITY 0x0
-
- Entry 208 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D00000
- (OFFSET, MASK, VALUE) (0XFF981340, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_208_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_208_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_208_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_208_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_208_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_208_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_208_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
- /*Register : APERPERM_209 @ 0XFF981344</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_209_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_209_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_209_PARITY 0x0
-
- Entry 209 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D10000
- (OFFSET, MASK, VALUE) (0XFF981344, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_209_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_209_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_209_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_209_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_209_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_209_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_209_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
- /*Register : APERPERM_210 @ 0XFF981348</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_210_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_210_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_210_PARITY 0x0
-
- Entry 210 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D20000
- (OFFSET, MASK, VALUE) (0XFF981348, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_210_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_210_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_210_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_210_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_210_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_210_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_210_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
- /*Register : APERPERM_211 @ 0XFF98134C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_211_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_211_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_211_PARITY 0x0
-
- Entry 211 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D30000
- (OFFSET, MASK, VALUE) (0XFF98134C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_211_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_211_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_211_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_211_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_211_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_211_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_211_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF
- /*Register : APERPERM_212 @ 0XFF981350</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_212_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_212_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_212_PARITY 0x0
-
- Entry 212 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D40000
- (OFFSET, MASK, VALUE) (0XFF981350, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_212_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_212_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_212_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_212_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_212_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_212_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_212_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF
- /*Register : APERPERM_213 @ 0XFF981354</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_213_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_213_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_213_PARITY 0x0
-
- Entry 213 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D50000
- (OFFSET, MASK, VALUE) (0XFF981354, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_213_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_213_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_213_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_213_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_213_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_213_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_213_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
- /*Register : APERPERM_214 @ 0XFF981358</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_214_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_214_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_214_PARITY 0x0
-
- Entry 214 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D60000
- (OFFSET, MASK, VALUE) (0XFF981358, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_214_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_214_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_214_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_214_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_214_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_214_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_214_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
- /*Register : APERPERM_215 @ 0XFF98135C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_215_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_215_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_215_PARITY 0x0
-
- Entry 215 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D70000
- (OFFSET, MASK, VALUE) (0XFF98135C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_215_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_215_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_215_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_215_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_215_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_215_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_215_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
- /*Register : APERPERM_216 @ 0XFF981360</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_216_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_216_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_216_PARITY 0x0
-
- Entry 216 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D80000
- (OFFSET, MASK, VALUE) (0XFF981360, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_216_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_216_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_216_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_216_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_216_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_216_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_216_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
- /*Register : APERPERM_217 @ 0XFF981364</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_217_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_217_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_217_PARITY 0x0
-
- Entry 217 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00D90000
- (OFFSET, MASK, VALUE) (0XFF981364, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_217_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_217_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_217_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_217_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_217_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_217_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_217_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
- /*Register : APERPERM_218 @ 0XFF981368</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_218_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_218_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_218_PARITY 0x0
-
- Entry 218 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00DA0000
- (OFFSET, MASK, VALUE) (0XFF981368, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_218_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_218_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_218_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_218_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_218_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_218_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_218_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
- /*Register : APERPERM_219 @ 0XFF98136C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_219_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_219_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_219_PARITY 0x0
-
- Entry 219 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00DB0000
- (OFFSET, MASK, VALUE) (0XFF98136C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_219_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_219_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_219_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_219_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_219_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_219_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_219_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
- /*Register : APERPERM_220 @ 0XFF981370</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_220_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_220_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_220_PARITY 0x0
-
- Entry 220 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00DC0000
- (OFFSET, MASK, VALUE) (0XFF981370, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_220_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_220_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_220_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_220_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_220_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_220_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_220_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
- /*Register : APERPERM_221 @ 0XFF981374</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_221_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_221_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_221_PARITY 0x0
-
- Entry 221 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00DD0000
- (OFFSET, MASK, VALUE) (0XFF981374, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_221_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_221_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_221_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_221_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_221_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_221_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_221_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
- /*Register : APERPERM_222 @ 0XFF981378</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_222_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_222_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_222_PARITY 0x0
-
- Entry 222 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00DE0000
- (OFFSET, MASK, VALUE) (0XFF981378, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_222_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_222_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_222_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_222_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_222_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_222_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_222_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
- /*Register : APERPERM_223 @ 0XFF98137C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_223_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_223_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_223_PARITY 0x0
-
- Entry 223 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00DF0000
- (OFFSET, MASK, VALUE) (0XFF98137C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_223_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_223_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_223_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_223_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_223_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_223_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_223_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF
- /*Register : APERPERM_224 @ 0XFF981380</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_224_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_224_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_224_PARITY 0x0
-
- Entry 224 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E00000
- (OFFSET, MASK, VALUE) (0XFF981380, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_224_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_224_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_224_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_224_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_224_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_224_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_224_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: FFE1FFFF
- /*Register : APERPERM_225 @ 0XFF981384</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_225_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_225_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_225_PARITY 0x0
-
- Entry 225 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E10000
- (OFFSET, MASK, VALUE) (0XFF981384, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_225_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_225_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_225_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_225_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_225_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_225_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_225_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF
- /*Register : APERPERM_226 @ 0XFF981388</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_226_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_226_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_226_PARITY 0x0
-
- Entry 226 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E20000
- (OFFSET, MASK, VALUE) (0XFF981388, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_226_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_226_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_226_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_226_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_226_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_226_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_226_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: FFE3FFFF
- /*Register : APERPERM_227 @ 0XFF98138C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_227_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_227_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_227_PARITY 0x0
-
- Entry 227 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E30000
- (OFFSET, MASK, VALUE) (0XFF98138C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_227_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_227_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_227_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_227_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_227_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_227_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_227_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDRESS: FFE4FFFF
- /*Register : APERPERM_228 @ 0XFF981390</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_228_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_228_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_228_PARITY 0x0
-
- Entry 228 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E40000
- (OFFSET, MASK, VALUE) (0XFF981390, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_228_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_228_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_228_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_228_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_228_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_228_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_228_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FFE5FFFF
- /*Register : APERPERM_229 @ 0XFF981394</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_229_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_229_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_229_PARITY 0x0
-
- Entry 229 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E50000
- (OFFSET, MASK, VALUE) (0XFF981394, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_229_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_229_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_229_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_229_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_229_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_229_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_229_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
- /*Register : APERPERM_230 @ 0XFF981398</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_230_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_230_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_230_PARITY 0x0
-
- Entry 230 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E60000
- (OFFSET, MASK, VALUE) (0XFF981398, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_230_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_230_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_230_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_230_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_230_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_230_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_230_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
- /*Register : APERPERM_231 @ 0XFF98139C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_231_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_231_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_231_PARITY 0x0
-
- Entry 231 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E70000
- (OFFSET, MASK, VALUE) (0XFF98139C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_231_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_231_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_231_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_231_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_231_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_231_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_231_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
- /*Register : APERPERM_232 @ 0XFF9813A0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_232_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_232_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_232_PARITY 0x0
-
- Entry 232 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E80000
- (OFFSET, MASK, VALUE) (0XFF9813A0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_232_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_232_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_232_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_232_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_232_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_232_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_232_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFFF
- /*Register : APERPERM_233 @ 0XFF9813A4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_233_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_233_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_233_PARITY 0x0
-
- Entry 233 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00E90000
- (OFFSET, MASK, VALUE) (0XFF9813A4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_233_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_233_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_233_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_233_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_233_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_233_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_233_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEAFFFF
- /*Register : APERPERM_234 @ 0XFF9813A8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_234_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_234_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_234_PARITY 0x0
-
- Entry 234 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00EA0000
- (OFFSET, MASK, VALUE) (0XFF9813A8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_234_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_234_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_234_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_234_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_234_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_234_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_234_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFFF
- /*Register : APERPERM_235 @ 0XFF9813AC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_235_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_235_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_235_PARITY 0x0
-
- Entry 235 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00EB0000
- (OFFSET, MASK, VALUE) (0XFF9813AC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_235_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_235_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_235_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_235_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_235_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_235_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_235_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDRESS: FFECFFFF
- /*Register : APERPERM_236 @ 0XFF9813B0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_236_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_236_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_236_PARITY 0x0
-
- Entry 236 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00EC0000
- (OFFSET, MASK, VALUE) (0XFF9813B0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_236_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_236_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_236_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_236_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_236_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_236_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_236_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FFEDFFFF
- /*Register : APERPERM_237 @ 0XFF9813B4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_237_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_237_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_237_PARITY 0x0
-
- Entry 237 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00ED0000
- (OFFSET, MASK, VALUE) (0XFF9813B4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_237_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_237_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_237_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_237_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_237_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_237_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_237_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_238 @ 0XFF9813B8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_238_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_238_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_238_PARITY 0x0
-
- Entry 238 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00EE0000
- (OFFSET, MASK, VALUE) (0XFF9813B8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_238_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_238_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_238_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_238_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_238_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_238_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_238_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_239 @ 0XFF9813BC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_239_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_239_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_239_PARITY 0x0
-
- Entry 239 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00EF0000
- (OFFSET, MASK, VALUE) (0XFF9813BC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_239_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_239_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_239_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_239_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_239_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_239_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_239_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_240 @ 0XFF9813C0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_240_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_240_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_240_PARITY 0x0
-
- Entry 240 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F00000
- (OFFSET, MASK, VALUE) (0XFF9813C0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_240_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_240_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_240_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_240_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_240_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_240_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_240_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_241 @ 0XFF9813C4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_241_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_241_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_241_PARITY 0x0
-
- Entry 241 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F10000
- (OFFSET, MASK, VALUE) (0XFF9813C4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_241_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_241_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_241_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_241_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_241_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_241_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_241_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_242 @ 0XFF9813C8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_242_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_242_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_242_PARITY 0x0
-
- Entry 242 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F20000
- (OFFSET, MASK, VALUE) (0XFF9813C8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_242_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_242_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_242_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_242_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_242_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_242_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_242_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_243 @ 0XFF9813CC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_243_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_243_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_243_PARITY 0x0
-
- Entry 243 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F30000
- (OFFSET, MASK, VALUE) (0XFF9813CC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_243_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_243_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_243_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_243_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_243_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_243_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_243_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_244 @ 0XFF9813D0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_244_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_244_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_244_PARITY 0x0
-
- Entry 244 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F40000
- (OFFSET, MASK, VALUE) (0XFF9813D0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_244_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_244_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_244_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_244_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_244_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_244_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_244_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_245 @ 0XFF9813D4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_245_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_245_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_245_PARITY 0x0
-
- Entry 245 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F50000
- (OFFSET, MASK, VALUE) (0XFF9813D4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_245_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_245_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_245_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_245_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_245_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_245_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_245_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_246 @ 0XFF9813D8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_246_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_246_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_246_PARITY 0x0
-
- Entry 246 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F60000
- (OFFSET, MASK, VALUE) (0XFF9813D8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_246_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_246_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_246_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_246_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_246_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_246_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_246_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_247 @ 0XFF9813DC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_247_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_247_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_247_PARITY 0x0
-
- Entry 247 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F70000
- (OFFSET, MASK, VALUE) (0XFF9813DC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_247_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_247_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_247_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_247_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_247_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_247_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_247_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_248 @ 0XFF9813E0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_248_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_248_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_248_PARITY 0x0
-
- Entry 248 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F80000
- (OFFSET, MASK, VALUE) (0XFF9813E0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_248_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_248_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_248_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_248_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_248_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_248_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_248_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_249 @ 0XFF9813E4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_249_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_249_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_249_PARITY 0x0
-
- Entry 249 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00F90000
- (OFFSET, MASK, VALUE) (0XFF9813E4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_249_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_249_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_249_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_249_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_249_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_249_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_249_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_250 @ 0XFF9813E8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_250_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_250_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_250_PARITY 0x0
-
- Entry 250 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00FA0000
- (OFFSET, MASK, VALUE) (0XFF9813E8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_250_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_250_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_250_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_250_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_250_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_250_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_250_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_251 @ 0XFF9813EC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_251_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_251_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_251_PARITY 0x0
-
- Entry 251 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00FB0000
- (OFFSET, MASK, VALUE) (0XFF9813EC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_251_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_251_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_251_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_251_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_251_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_251_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_251_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
- /*Register : APERPERM_252 @ 0XFF9813F0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_252_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_252_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_252_PARITY 0x0
-
- Entry 252 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00FC0000
- (OFFSET, MASK, VALUE) (0XFF9813F0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_252_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_252_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_252_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_252_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_252_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_252_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_252_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
- // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
- // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_256 @ 0XFF981400</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_256_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_256_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_256_PARITY 0x0
-
- Entry 256 of the Aperture Permission List, for 32-byte IPI buffer 000 at BASE_32B + 0x00000000
- (OFFSET, MASK, VALUE) (0XFF981400, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_256_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_256_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_257 @ 0XFF981404</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_257_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_257_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_257_PARITY 0x0
-
- Entry 257 of the Aperture Permission List, for 32-byte IPI buffer 001 at BASE_32B + 0x00000020
- (OFFSET, MASK, VALUE) (0XFF981404, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_257_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_257_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_258 @ 0XFF981408</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_258_PERMISSION 0x48
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_258_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_258_PARITY 0x0
-
- Entry 258 of the Aperture Permission List, for 32-byte IPI buffer 002 at BASE_32B + 0x00000040
- (OFFSET, MASK, VALUE) (0XFF981408, 0xF80FFFFFU ,0x08000048U)
- RegMask = (LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_258_PARITY_MASK | 0 );
-
- RegVal = ((0x00000048U << LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_258_OFFSET ,0xF80FFFFFU ,0x08000048U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_259 @ 0XFF98140C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_259_PERMISSION 0x84
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_259_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_259_PARITY 0x0
-
- Entry 259 of the Aperture Permission List, for 32-byte IPI buffer 003 at BASE_32B + 0x00000060
- (OFFSET, MASK, VALUE) (0XFF98140C, 0xF80FFFFFU ,0x08000084U)
- RegMask = (LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_259_PARITY_MASK | 0 );
-
- RegVal = ((0x00000084U << LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_259_OFFSET ,0xF80FFFFFU ,0x08000084U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_260 @ 0XFF981410</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_260_PERMISSION 0x41
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_260_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_260_PARITY 0x0
-
- Entry 260 of the Aperture Permission List, for 32-byte IPI buffer 004 at BASE_32B + 0x00000080
- (OFFSET, MASK, VALUE) (0XFF981410, 0xF80FFFFFU ,0x08000041U)
- RegMask = (LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_260_PARITY_MASK | 0 );
-
- RegVal = ((0x00000041U << LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_260_OFFSET ,0xF80FFFFFU ,0x08000041U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_261 @ 0XFF981414</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_261_PERMISSION 0x14
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_261_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_261_PARITY 0x0
-
- Entry 261 of the Aperture Permission List, for 32-byte IPI buffer 005 at BASE_32B + 0x000000A0
- (OFFSET, MASK, VALUE) (0XFF981414, 0xF80FFFFFU ,0x08000014U)
- RegMask = (LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_261_PARITY_MASK | 0 );
-
- RegVal = ((0x00000014U << LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_261_OFFSET ,0xF80FFFFFU ,0x08000014U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_262 @ 0XFF981418</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_262_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_262_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_262_PARITY 0x0
-
- Entry 262 of the Aperture Permission List, for 32-byte IPI buffer 006 at BASE_32B + 0x000000C0
- (OFFSET, MASK, VALUE) (0XFF981418, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_262_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_262_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_263 @ 0XFF98141C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_263_PERMISSION 0x4
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_263_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_263_PARITY 0x0
-
- Entry 263 of the Aperture Permission List, for 32-byte IPI buffer 007 at BASE_32B + 0x000000E0
- (OFFSET, MASK, VALUE) (0XFF98141C, 0xF80FFFFFU ,0x08000004U)
- RegMask = (LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_263_PARITY_MASK | 0 );
-
- RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_263_OFFSET ,0xF80FFFFFU ,0x08000004U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_264 @ 0XFF981420</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_264_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_264_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_264_PARITY 0x0
-
- Entry 264 of the Aperture Permission List, for 32-byte IPI buffer 008 at BASE_32B + 0x00000100
- (OFFSET, MASK, VALUE) (0XFF981420, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_264_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_264_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_265 @ 0XFF981424</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_265_PERMISSION 0x4
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_265_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_265_PARITY 0x0
-
- Entry 265 of the Aperture Permission List, for 32-byte IPI buffer 009 at BASE_32B + 0x00000120
- (OFFSET, MASK, VALUE) (0XFF981424, 0xF80FFFFFU ,0x08000004U)
- RegMask = (LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_265_PARITY_MASK | 0 );
-
- RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_265_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_265_OFFSET ,0xF80FFFFFU ,0x08000004U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_266 @ 0XFF981428</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_266_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_266_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_266_PARITY 0x0
-
- Entry 266 of the Aperture Permission List, for 32-byte IPI buffer 010 at BASE_32B + 0x00000140
- (OFFSET, MASK, VALUE) (0XFF981428, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_266_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_266_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_266_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_266_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_266_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_267 @ 0XFF98142C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_267_PERMISSION 0x4
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_267_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_267_PARITY 0x0
-
- Entry 267 of the Aperture Permission List, for 32-byte IPI buffer 011 at BASE_32B + 0x00000160
- (OFFSET, MASK, VALUE) (0XFF98142C, 0xF80FFFFFU ,0x08000004U)
- RegMask = (LPD_XPPU_CFG_APERPERM_267_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_267_PARITY_MASK | 0 );
-
- RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_267_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_267_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_267_OFFSET ,0xF80FFFFFU ,0x08000004U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_268 @ 0XFF981430</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_268_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_268_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_268_PARITY 0x0
-
- Entry 268 of the Aperture Permission List, for 32-byte IPI buffer 012 at BASE_32B + 0x00000180
- (OFFSET, MASK, VALUE) (0XFF981430, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_268_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_268_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_268_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_268_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_268_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_269 @ 0XFF981434</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_269_PERMISSION 0x4
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_269_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_269_PARITY 0x0
-
- Entry 269 of the Aperture Permission List, for 32-byte IPI buffer 013 at BASE_32B + 0x000001A0
- (OFFSET, MASK, VALUE) (0XFF981434, 0xF80FFFFFU ,0x08000004U)
- RegMask = (LPD_XPPU_CFG_APERPERM_269_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_269_PARITY_MASK | 0 );
-
- RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_269_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_269_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_269_OFFSET ,0xF80FFFFFU ,0x08000004U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_270 @ 0XFF981438</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_270_PERMISSION 0x42
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_270_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_270_PARITY 0x0
-
- Entry 270 of the Aperture Permission List, for 32-byte IPI buffer 014 at BASE_32B + 0x000001C0
- (OFFSET, MASK, VALUE) (0XFF981438, 0xF80FFFFFU ,0x08000042U)
- RegMask = (LPD_XPPU_CFG_APERPERM_270_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_270_PARITY_MASK | 0 );
-
- RegVal = ((0x00000042U << LPD_XPPU_CFG_APERPERM_270_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_270_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_270_OFFSET ,0xF80FFFFFU ,0x08000042U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
- /*Register : APERPERM_271 @ 0XFF98143C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_271_PERMISSION 0x24
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_271_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_271_PARITY 0x0
-
- Entry 271 of the Aperture Permission List, for 32-byte IPI buffer 015 at BASE_32B + 0x000001E0
- (OFFSET, MASK, VALUE) (0XFF98143C, 0xF80FFFFFU ,0x08000024U)
- RegMask = (LPD_XPPU_CFG_APERPERM_271_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_271_PARITY_MASK | 0 );
-
- RegVal = ((0x00000024U << LPD_XPPU_CFG_APERPERM_271_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_271_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_271_OFFSET ,0xF80FFFFFU ,0x08000024U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_272 @ 0XFF981440</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_272_PERMISSION 0x84
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_272_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_272_PARITY 0x0
-
- Entry 272 of the Aperture Permission List, for 32-byte IPI buffer 016 at BASE_32B + 0x00000200
- (OFFSET, MASK, VALUE) (0XFF981440, 0xF80FFFFFU ,0x08000084U)
- RegMask = (LPD_XPPU_CFG_APERPERM_272_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_272_PARITY_MASK | 0 );
-
- RegVal = ((0x00000084U << LPD_XPPU_CFG_APERPERM_272_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_272_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_272_OFFSET ,0xF80FFFFFU ,0x08000084U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_273 @ 0XFF981444</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_273_PERMISSION 0x48
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_273_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_273_PARITY 0x0
-
- Entry 273 of the Aperture Permission List, for 32-byte IPI buffer 017 at BASE_32B + 0x00000220
- (OFFSET, MASK, VALUE) (0XFF981444, 0xF80FFFFFU ,0x08000048U)
- RegMask = (LPD_XPPU_CFG_APERPERM_273_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_273_PARITY_MASK | 0 );
-
- RegVal = ((0x00000048U << LPD_XPPU_CFG_APERPERM_273_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_273_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_273_OFFSET ,0xF80FFFFFU ,0x08000048U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_274 @ 0XFF981448</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_274_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_274_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_274_PARITY 0x0
-
- Entry 274 of the Aperture Permission List, for 32-byte IPI buffer 018 at BASE_32B + 0x00000240
- (OFFSET, MASK, VALUE) (0XFF981448, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_274_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_274_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_274_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_274_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_274_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_275 @ 0XFF98144C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_275_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_275_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_275_PARITY 0x0
-
- Entry 275 of the Aperture Permission List, for 32-byte IPI buffer 019 at BASE_32B + 0x00000260
- (OFFSET, MASK, VALUE) (0XFF98144C, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_275_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_275_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_275_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_275_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_275_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_276 @ 0XFF981450</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_276_PERMISSION 0x81
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_276_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_276_PARITY 0x0
-
- Entry 276 of the Aperture Permission List, for 32-byte IPI buffer 020 at BASE_32B + 0x00000280
- (OFFSET, MASK, VALUE) (0XFF981450, 0xF80FFFFFU ,0x08000081U)
- RegMask = (LPD_XPPU_CFG_APERPERM_276_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_276_PARITY_MASK | 0 );
-
- RegVal = ((0x00000081U << LPD_XPPU_CFG_APERPERM_276_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_276_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_276_OFFSET ,0xF80FFFFFU ,0x08000081U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_277 @ 0XFF981454</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_277_PERMISSION 0x18
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_277_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_277_PARITY 0x0
-
- Entry 277 of the Aperture Permission List, for 32-byte IPI buffer 021 at BASE_32B + 0x000002A0
- (OFFSET, MASK, VALUE) (0XFF981454, 0xF80FFFFFU ,0x08000018U)
- RegMask = (LPD_XPPU_CFG_APERPERM_277_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_277_PARITY_MASK | 0 );
-
- RegVal = ((0x00000018U << LPD_XPPU_CFG_APERPERM_277_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_277_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_277_OFFSET ,0xF80FFFFFU ,0x08000018U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_278 @ 0XFF981458</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_278_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_278_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_278_PARITY 0x0
-
- Entry 278 of the Aperture Permission List, for 32-byte IPI buffer 022 at BASE_32B + 0x000002C0
- (OFFSET, MASK, VALUE) (0XFF981458, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_278_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_278_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_278_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_278_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_278_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_279 @ 0XFF98145C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_279_PERMISSION 0x8
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_279_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_279_PARITY 0x0
-
- Entry 279 of the Aperture Permission List, for 32-byte IPI buffer 023 at BASE_32B + 0x000002E0
- (OFFSET, MASK, VALUE) (0XFF98145C, 0xF80FFFFFU ,0x08000008U)
- RegMask = (LPD_XPPU_CFG_APERPERM_279_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_279_PARITY_MASK | 0 );
-
- RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_279_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_279_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_279_OFFSET ,0xF80FFFFFU ,0x08000008U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_280 @ 0XFF981460</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_280_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_280_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_280_PARITY 0x0
-
- Entry 280 of the Aperture Permission List, for 32-byte IPI buffer 024 at BASE_32B + 0x00000300
- (OFFSET, MASK, VALUE) (0XFF981460, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_280_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_280_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_280_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_280_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_280_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_281 @ 0XFF981464</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_281_PERMISSION 0x8
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_281_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_281_PARITY 0x0
-
- Entry 281 of the Aperture Permission List, for 32-byte IPI buffer 025 at BASE_32B + 0x00000320
- (OFFSET, MASK, VALUE) (0XFF981464, 0xF80FFFFFU ,0x08000008U)
- RegMask = (LPD_XPPU_CFG_APERPERM_281_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_281_PARITY_MASK | 0 );
-
- RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_281_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_281_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_281_OFFSET ,0xF80FFFFFU ,0x08000008U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_282 @ 0XFF981468</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_282_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_282_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_282_PARITY 0x0
-
- Entry 282 of the Aperture Permission List, for 32-byte IPI buffer 026 at BASE_32B + 0x00000340
- (OFFSET, MASK, VALUE) (0XFF981468, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_282_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_282_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_282_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_282_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_282_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_283 @ 0XFF98146C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_283_PERMISSION 0x8
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_283_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_283_PARITY 0x0
-
- Entry 283 of the Aperture Permission List, for 32-byte IPI buffer 027 at BASE_32B + 0x00000360
- (OFFSET, MASK, VALUE) (0XFF98146C, 0xF80FFFFFU ,0x08000008U)
- RegMask = (LPD_XPPU_CFG_APERPERM_283_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_283_PARITY_MASK | 0 );
-
- RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_283_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_283_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_283_OFFSET ,0xF80FFFFFU ,0x08000008U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_284 @ 0XFF981470</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_284_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_284_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_284_PARITY 0x0
-
- Entry 284 of the Aperture Permission List, for 32-byte IPI buffer 028 at BASE_32B + 0x00000380
- (OFFSET, MASK, VALUE) (0XFF981470, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_284_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_284_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_284_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_284_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_284_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_285 @ 0XFF981474</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_285_PERMISSION 0x8
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_285_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_285_PARITY 0x0
-
- Entry 285 of the Aperture Permission List, for 32-byte IPI buffer 029 at BASE_32B + 0x000003A0
- (OFFSET, MASK, VALUE) (0XFF981474, 0xF80FFFFFU ,0x08000008U)
- RegMask = (LPD_XPPU_CFG_APERPERM_285_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_285_PARITY_MASK | 0 );
-
- RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_285_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_285_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_285_OFFSET ,0xF80FFFFFU ,0x08000008U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_286 @ 0XFF981478</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_286_PERMISSION 0x82
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_286_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_286_PARITY 0x0
-
- Entry 286 of the Aperture Permission List, for 32-byte IPI buffer 030 at BASE_32B + 0x000003C0
- (OFFSET, MASK, VALUE) (0XFF981478, 0xF80FFFFFU ,0x08000082U)
- RegMask = (LPD_XPPU_CFG_APERPERM_286_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_286_PARITY_MASK | 0 );
-
- RegVal = ((0x00000082U << LPD_XPPU_CFG_APERPERM_286_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_286_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_286_OFFSET ,0xF80FFFFFU ,0x08000082U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
- /*Register : APERPERM_287 @ 0XFF98147C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_287_PERMISSION 0x28
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_287_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_287_PARITY 0x0
-
- Entry 287 of the Aperture Permission List, for 32-byte IPI buffer 031 at BASE_32B + 0x000003E0
- (OFFSET, MASK, VALUE) (0XFF98147C, 0xF80FFFFFU ,0x08000028U)
- RegMask = (LPD_XPPU_CFG_APERPERM_287_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_287_PARITY_MASK | 0 );
-
- RegVal = ((0x00000028U << LPD_XPPU_CFG_APERPERM_287_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_287_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_287_OFFSET ,0xF80FFFFFU ,0x08000028U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_288 @ 0XFF981480</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_288_PERMISSION 0x14
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_288_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_288_PARITY 0x0
-
- Entry 288 of the Aperture Permission List, for 32-byte IPI buffer 032 at BASE_32B + 0x00000400
- (OFFSET, MASK, VALUE) (0XFF981480, 0xF80FFFFFU ,0x08000014U)
- RegMask = (LPD_XPPU_CFG_APERPERM_288_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_288_PARITY_MASK | 0 );
-
- RegVal = ((0x00000014U << LPD_XPPU_CFG_APERPERM_288_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_288_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_288_OFFSET ,0xF80FFFFFU ,0x08000014U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_289 @ 0XFF981484</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_289_PERMISSION 0x41
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_289_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_289_PARITY 0x0
-
- Entry 289 of the Aperture Permission List, for 32-byte IPI buffer 033 at BASE_32B + 0x00000420
- (OFFSET, MASK, VALUE) (0XFF981484, 0xF80FFFFFU ,0x08000041U)
- RegMask = (LPD_XPPU_CFG_APERPERM_289_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_289_PARITY_MASK | 0 );
-
- RegVal = ((0x00000041U << LPD_XPPU_CFG_APERPERM_289_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_289_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_289_OFFSET ,0xF80FFFFFU ,0x08000041U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_290 @ 0XFF981488</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_290_PERMISSION 0x18
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_290_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_290_PARITY 0x0
-
- Entry 290 of the Aperture Permission List, for 32-byte IPI buffer 034 at BASE_32B + 0x00000440
- (OFFSET, MASK, VALUE) (0XFF981488, 0xF80FFFFFU ,0x08000018U)
- RegMask = (LPD_XPPU_CFG_APERPERM_290_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_290_PARITY_MASK | 0 );
-
- RegVal = ((0x00000018U << LPD_XPPU_CFG_APERPERM_290_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_290_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_290_OFFSET ,0xF80FFFFFU ,0x08000018U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_291 @ 0XFF98148C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_291_PERMISSION 0x81
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_291_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_291_PARITY 0x0
-
- Entry 291 of the Aperture Permission List, for 32-byte IPI buffer 035 at BASE_32B + 0x00000460
- (OFFSET, MASK, VALUE) (0XFF98148C, 0xF80FFFFFU ,0x08000081U)
- RegMask = (LPD_XPPU_CFG_APERPERM_291_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_291_PARITY_MASK | 0 );
-
- RegVal = ((0x00000081U << LPD_XPPU_CFG_APERPERM_291_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_291_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_291_OFFSET ,0xF80FFFFFU ,0x08000081U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_292 @ 0XFF981490</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_292_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_292_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_292_PARITY 0x0
-
- Entry 292 of the Aperture Permission List, for 32-byte IPI buffer 036 at BASE_32B + 0x00000480
- (OFFSET, MASK, VALUE) (0XFF981490, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_292_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_292_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_292_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_292_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_292_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_293 @ 0XFF981494</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_293_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_293_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_293_PARITY 0x0
-
- Entry 293 of the Aperture Permission List, for 32-byte IPI buffer 037 at BASE_32B + 0x000004A0
- (OFFSET, MASK, VALUE) (0XFF981494, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_293_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_293_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_293_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_293_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_293_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_294 @ 0XFF981498</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_294_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_294_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_294_PARITY 0x0
-
- Entry 294 of the Aperture Permission List, for 32-byte IPI buffer 038 at BASE_32B + 0x000004C0
- (OFFSET, MASK, VALUE) (0XFF981498, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_294_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_294_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_294_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_294_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_294_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_295 @ 0XFF98149C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_295_PERMISSION 0x1
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_295_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_295_PARITY 0x0
-
- Entry 295 of the Aperture Permission List, for 32-byte IPI buffer 039 at BASE_32B + 0x000004E0
- (OFFSET, MASK, VALUE) (0XFF98149C, 0xF80FFFFFU ,0x08000001U)
- RegMask = (LPD_XPPU_CFG_APERPERM_295_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_295_PARITY_MASK | 0 );
-
- RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_295_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_295_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_295_OFFSET ,0xF80FFFFFU ,0x08000001U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_296 @ 0XFF9814A0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_296_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_296_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_296_PARITY 0x0
-
- Entry 296 of the Aperture Permission List, for 32-byte IPI buffer 040 at BASE_32B + 0x00000500
- (OFFSET, MASK, VALUE) (0XFF9814A0, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_296_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_296_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_296_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_296_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_296_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_297 @ 0XFF9814A4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_297_PERMISSION 0x1
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_297_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_297_PARITY 0x0
-
- Entry 297 of the Aperture Permission List, for 32-byte IPI buffer 041 at BASE_32B + 0x00000520
- (OFFSET, MASK, VALUE) (0XFF9814A4, 0xF80FFFFFU ,0x08000001U)
- RegMask = (LPD_XPPU_CFG_APERPERM_297_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_297_PARITY_MASK | 0 );
-
- RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_297_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_297_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_297_OFFSET ,0xF80FFFFFU ,0x08000001U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_298 @ 0XFF9814A8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_298_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_298_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_298_PARITY 0x0
-
- Entry 298 of the Aperture Permission List, for 32-byte IPI buffer 042 at BASE_32B + 0x00000540
- (OFFSET, MASK, VALUE) (0XFF9814A8, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_298_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_298_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_298_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_298_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_298_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_299 @ 0XFF9814AC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_299_PERMISSION 0x1
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_299_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_299_PARITY 0x0
-
- Entry 299 of the Aperture Permission List, for 32-byte IPI buffer 043 at BASE_32B + 0x00000560
- (OFFSET, MASK, VALUE) (0XFF9814AC, 0xF80FFFFFU ,0x08000001U)
- RegMask = (LPD_XPPU_CFG_APERPERM_299_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_299_PARITY_MASK | 0 );
-
- RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_299_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_299_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_299_OFFSET ,0xF80FFFFFU ,0x08000001U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_300 @ 0XFF9814B0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_300_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_300_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_300_PARITY 0x0
-
- Entry 300 of the Aperture Permission List, for 32-byte IPI buffer 044 at BASE_32B + 0x00000580
- (OFFSET, MASK, VALUE) (0XFF9814B0, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_300_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_300_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_300_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_300_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_300_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_301 @ 0XFF9814B4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_301_PERMISSION 0x1
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_301_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_301_PARITY 0x0
-
- Entry 301 of the Aperture Permission List, for 32-byte IPI buffer 045 at BASE_32B + 0x000005A0
- (OFFSET, MASK, VALUE) (0XFF9814B4, 0xF80FFFFFU ,0x08000001U)
- RegMask = (LPD_XPPU_CFG_APERPERM_301_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_301_PARITY_MASK | 0 );
-
- RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_301_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_301_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_301_OFFSET ,0xF80FFFFFU ,0x08000001U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_302 @ 0XFF9814B8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_302_PERMISSION 0x12
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_302_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_302_PARITY 0x0
-
- Entry 302 of the Aperture Permission List, for 32-byte IPI buffer 046 at BASE_32B + 0x000005C0
- (OFFSET, MASK, VALUE) (0XFF9814B8, 0xF80FFFFFU ,0x08000012U)
- RegMask = (LPD_XPPU_CFG_APERPERM_302_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_302_PARITY_MASK | 0 );
-
- RegVal = ((0x00000012U << LPD_XPPU_CFG_APERPERM_302_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_302_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_302_OFFSET ,0xF80FFFFFU ,0x08000012U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
- /*Register : APERPERM_303 @ 0XFF9814BC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_303_PERMISSION 0x21
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_303_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_303_PARITY 0x0
-
- Entry 303 of the Aperture Permission List, for 32-byte IPI buffer 047 at BASE_32B + 0x000005E0
- (OFFSET, MASK, VALUE) (0XFF9814BC, 0xF80FFFFFU ,0x08000021U)
- RegMask = (LPD_XPPU_CFG_APERPERM_303_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_303_PARITY_MASK | 0 );
-
- RegVal = ((0x00000021U << LPD_XPPU_CFG_APERPERM_303_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_303_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_303_OFFSET ,0xF80FFFFFU ,0x08000021U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_304 @ 0XFF9814C0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_304_PERMISSION 0x4
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_304_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_304_PARITY 0x0
-
- Entry 304 of the Aperture Permission List, for 32-byte IPI buffer 048 at BASE_32B + 0x00000600
- (OFFSET, MASK, VALUE) (0XFF9814C0, 0xF80FFFFFU ,0x08000004U)
- RegMask = (LPD_XPPU_CFG_APERPERM_304_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_304_PARITY_MASK | 0 );
-
- RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_304_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_304_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_304_OFFSET ,0xF80FFFFFU ,0x08000004U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_305 @ 0XFF9814C4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_305_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_305_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_305_PARITY 0x0
-
- Entry 305 of the Aperture Permission List, for 32-byte IPI buffer 049 at BASE_32B + 0x00000620
- (OFFSET, MASK, VALUE) (0XFF9814C4, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_305_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_305_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_305_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_305_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_305_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_306 @ 0XFF9814C8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_306_PERMISSION 0x8
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_306_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_306_PARITY 0x0
-
- Entry 306 of the Aperture Permission List, for 32-byte IPI buffer 050 at BASE_32B + 0x00000640
- (OFFSET, MASK, VALUE) (0XFF9814C8, 0xF80FFFFFU ,0x08000008U)
- RegMask = (LPD_XPPU_CFG_APERPERM_306_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_306_PARITY_MASK | 0 );
-
- RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_306_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_306_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_306_OFFSET ,0xF80FFFFFU ,0x08000008U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_307 @ 0XFF9814CC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_307_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_307_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_307_PARITY 0x0
-
- Entry 307 of the Aperture Permission List, for 32-byte IPI buffer 051 at BASE_32B + 0x00000660
- (OFFSET, MASK, VALUE) (0XFF9814CC, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_307_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_307_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_307_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_307_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_307_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_308 @ 0XFF9814D0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_308_PERMISSION 0x1
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_308_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_308_PARITY 0x0
-
- Entry 308 of the Aperture Permission List, for 32-byte IPI buffer 052 at BASE_32B + 0x00000680
- (OFFSET, MASK, VALUE) (0XFF9814D0, 0xF80FFFFFU ,0x08000001U)
- RegMask = (LPD_XPPU_CFG_APERPERM_308_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_308_PARITY_MASK | 0 );
-
- RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_308_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_308_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_308_OFFSET ,0xF80FFFFFU ,0x08000001U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_309 @ 0XFF9814D4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_309_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_309_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_309_PARITY 0x0
-
- Entry 309 of the Aperture Permission List, for 32-byte IPI buffer 053 at BASE_32B + 0x000006A0
- (OFFSET, MASK, VALUE) (0XFF9814D4, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_309_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_309_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_309_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_309_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_309_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_310 @ 0XFF9814D8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_310_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_310_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_310_PARITY 0x0
-
- Entry 310 of the Aperture Permission List, for 32-byte IPI buffer 054 at BASE_32B + 0x000006C0
- (OFFSET, MASK, VALUE) (0XFF9814D8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_310_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_310_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_310_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_310_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_310_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_310_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_310_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_311 @ 0XFF9814DC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_311_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_311_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_311_PARITY 0x0
-
- Entry 311 of the Aperture Permission List, for 32-byte IPI buffer 055 at BASE_32B + 0x000006E0
- (OFFSET, MASK, VALUE) (0XFF9814DC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_311_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_311_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_311_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_311_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_311_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_311_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_311_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_312 @ 0XFF9814E0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_312_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_312_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_312_PARITY 0x0
-
- Entry 312 of the Aperture Permission List, for 32-byte IPI buffer 056 at BASE_32B + 0x00000700
- (OFFSET, MASK, VALUE) (0XFF9814E0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_312_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_312_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_312_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_312_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_312_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_312_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_312_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_313 @ 0XFF9814E4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_313_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_313_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_313_PARITY 0x0
-
- Entry 313 of the Aperture Permission List, for 32-byte IPI buffer 057 at BASE_32B + 0x00000720
- (OFFSET, MASK, VALUE) (0XFF9814E4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_313_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_313_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_313_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_313_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_313_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_313_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_313_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_314 @ 0XFF9814E8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_314_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_314_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_314_PARITY 0x0
-
- Entry 314 of the Aperture Permission List, for 32-byte IPI buffer 058 at BASE_32B + 0x00000740
- (OFFSET, MASK, VALUE) (0XFF9814E8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_314_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_314_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_314_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_314_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_314_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_314_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_314_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_315 @ 0XFF9814EC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_315_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_315_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_315_PARITY 0x0
-
- Entry 315 of the Aperture Permission List, for 32-byte IPI buffer 059 at BASE_32B + 0x00000760
- (OFFSET, MASK, VALUE) (0XFF9814EC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_315_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_315_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_315_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_315_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_315_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_315_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_315_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_316 @ 0XFF9814F0</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_316_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_316_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_316_PARITY 0x0
-
- Entry 316 of the Aperture Permission List, for 32-byte IPI buffer 060 at BASE_32B + 0x00000780
- (OFFSET, MASK, VALUE) (0XFF9814F0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_316_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_316_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_316_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_316_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_316_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_316_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_316_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_317 @ 0XFF9814F4</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_317_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_317_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_317_PARITY 0x0
-
- Entry 317 of the Aperture Permission List, for 32-byte IPI buffer 061 at BASE_32B + 0x000007A0
- (OFFSET, MASK, VALUE) (0XFF9814F4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_317_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_317_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_317_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_317_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_317_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_317_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_317_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_318 @ 0XFF9814F8</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_318_PERMISSION 0x2
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_318_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_318_PARITY 0x0
-
- Entry 318 of the Aperture Permission List, for 32-byte IPI buffer 062 at BASE_32B + 0x000007C0
- (OFFSET, MASK, VALUE) (0XFF9814F8, 0xF80FFFFFU ,0x08000002U)
- RegMask = (LPD_XPPU_CFG_APERPERM_318_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_318_PARITY_MASK | 0 );
-
- RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_318_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_318_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_318_OFFSET ,0xF80FFFFFU ,0x08000002U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
- /*Register : APERPERM_319 @ 0XFF9814FC</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_319_PERMISSION 0x20
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_319_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_319_PARITY 0x0
-
- Entry 319 of the Aperture Permission List, for 32-byte IPI buffer 063 at BASE_32B + 0x000007E0
- (OFFSET, MASK, VALUE) (0XFF9814FC, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_319_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_319_PARITY_MASK | 0 );
-
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_319_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_319_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_319_OFFSET ,0xF80FFFFFU ,0x08000020U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_320 @ 0XFF981500</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_320_PERMISSION 0x4
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_320_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_320_PARITY 0x0
-
- Entry 320 of the Aperture Permission List, for 32-byte IPI buffer 064 at BASE_32B + 0x00000800
- (OFFSET, MASK, VALUE) (0XFF981500, 0xF80FFFFFU ,0x08000004U)
- RegMask = (LPD_XPPU_CFG_APERPERM_320_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_320_PARITY_MASK | 0 );
-
- RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_320_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_320_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_320_OFFSET ,0xF80FFFFFU ,0x08000004U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_321 @ 0XFF981504</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_321_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_321_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_321_PARITY 0x0
-
- Entry 321 of the Aperture Permission List, for 32-byte IPI buffer 065 at BASE_32B + 0x00000820
- (OFFSET, MASK, VALUE) (0XFF981504, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_321_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_321_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_321_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_321_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_321_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_322 @ 0XFF981508</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_322_PERMISSION 0x8
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_322_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_322_PARITY 0x0
-
- Entry 322 of the Aperture Permission List, for 32-byte IPI buffer 066 at BASE_32B + 0x00000840
- (OFFSET, MASK, VALUE) (0XFF981508, 0xF80FFFFFU ,0x08000008U)
- RegMask = (LPD_XPPU_CFG_APERPERM_322_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_322_PARITY_MASK | 0 );
-
- RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_322_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_322_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_322_OFFSET ,0xF80FFFFFU ,0x08000008U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_323 @ 0XFF98150C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_323_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_323_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_323_PARITY 0x0
-
- Entry 323 of the Aperture Permission List, for 32-byte IPI buffer 067 at BASE_32B + 0x00000860
- (OFFSET, MASK, VALUE) (0XFF98150C, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_323_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_323_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_323_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_323_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_323_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_324 @ 0XFF981510</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_324_PERMISSION 0x1
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_324_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_324_PARITY 0x0
-
- Entry 324 of the Aperture Permission List, for 32-byte IPI buffer 068 at BASE_32B + 0x00000880
- (OFFSET, MASK, VALUE) (0XFF981510, 0xF80FFFFFU ,0x08000001U)
- RegMask = (LPD_XPPU_CFG_APERPERM_324_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_324_PARITY_MASK | 0 );
-
- RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_324_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_324_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_324_OFFSET ,0xF80FFFFFU ,0x08000001U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_325 @ 0XFF981514</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_325_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_325_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_325_PARITY 0x0
-
- Entry 325 of the Aperture Permission List, for 32-byte IPI buffer 069 at BASE_32B + 0x000008A0
- (OFFSET, MASK, VALUE) (0XFF981514, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_325_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_325_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_325_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_325_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_325_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_326 @ 0XFF981518</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_326_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_326_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_326_PARITY 0x0
-
- Entry 326 of the Aperture Permission List, for 32-byte IPI buffer 070 at BASE_32B + 0x000008C0
- (OFFSET, MASK, VALUE) (0XFF981518, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_326_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_326_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_326_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_326_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_326_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_326_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_326_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_327 @ 0XFF98151C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_327_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_327_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_327_PARITY 0x0
-
- Entry 327 of the Aperture Permission List, for 32-byte IPI buffer 071 at BASE_32B + 0x000008E0
- (OFFSET, MASK, VALUE) (0XFF98151C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_327_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_327_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_327_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_327_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_327_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_327_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_327_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_328 @ 0XFF981520</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_328_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_328_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_328_PARITY 0x0
-
- Entry 328 of the Aperture Permission List, for 32-byte IPI buffer 072 at BASE_32B + 0x00000900
- (OFFSET, MASK, VALUE) (0XFF981520, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_328_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_328_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_328_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_328_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_328_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_328_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_328_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_329 @ 0XFF981524</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_329_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_329_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_329_PARITY 0x0
-
- Entry 329 of the Aperture Permission List, for 32-byte IPI buffer 073 at BASE_32B + 0x00000920
- (OFFSET, MASK, VALUE) (0XFF981524, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_329_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_329_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_329_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_329_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_329_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_329_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_329_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_330 @ 0XFF981528</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_330_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_330_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_330_PARITY 0x0
-
- Entry 330 of the Aperture Permission List, for 32-byte IPI buffer 074 at BASE_32B + 0x00000940
- (OFFSET, MASK, VALUE) (0XFF981528, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_330_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_330_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_330_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_330_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_330_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_330_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_330_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_331 @ 0XFF98152C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_331_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_331_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_331_PARITY 0x0
-
- Entry 331 of the Aperture Permission List, for 32-byte IPI buffer 075 at BASE_32B + 0x00000960
- (OFFSET, MASK, VALUE) (0XFF98152C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_331_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_331_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_331_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_331_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_331_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_331_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_331_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_332 @ 0XFF981530</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_332_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_332_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_332_PARITY 0x0
-
- Entry 332 of the Aperture Permission List, for 32-byte IPI buffer 076 at BASE_32B + 0x00000980
- (OFFSET, MASK, VALUE) (0XFF981530, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_332_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_332_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_332_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_332_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_332_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_332_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_332_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_333 @ 0XFF981534</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_333_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_333_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_333_PARITY 0x0
-
- Entry 333 of the Aperture Permission List, for 32-byte IPI buffer 077 at BASE_32B + 0x000009A0
- (OFFSET, MASK, VALUE) (0XFF981534, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_333_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_333_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_333_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_333_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_333_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_333_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_333_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_334 @ 0XFF981538</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_334_PERMISSION 0x2
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_334_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_334_PARITY 0x0
-
- Entry 334 of the Aperture Permission List, for 32-byte IPI buffer 078 at BASE_32B + 0x000009C0
- (OFFSET, MASK, VALUE) (0XFF981538, 0xF80FFFFFU ,0x08000002U)
- RegMask = (LPD_XPPU_CFG_APERPERM_334_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_334_PARITY_MASK | 0 );
-
- RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_334_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_334_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_334_OFFSET ,0xF80FFFFFU ,0x08000002U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
- /*Register : APERPERM_335 @ 0XFF98153C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_335_PERMISSION 0x20
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_335_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_335_PARITY 0x0
-
- Entry 335 of the Aperture Permission List, for 32-byte IPI buffer 079 at BASE_32B + 0x000009E0
- (OFFSET, MASK, VALUE) (0XFF98153C, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_335_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_335_PARITY_MASK | 0 );
-
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_335_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_335_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_335_OFFSET ,0xF80FFFFFU ,0x08000020U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_336 @ 0XFF981540</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_336_PERMISSION 0x4
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_336_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_336_PARITY 0x0
-
- Entry 336 of the Aperture Permission List, for 32-byte IPI buffer 080 at BASE_32B + 0x00000A00
- (OFFSET, MASK, VALUE) (0XFF981540, 0xF80FFFFFU ,0x08000004U)
- RegMask = (LPD_XPPU_CFG_APERPERM_336_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_336_PARITY_MASK | 0 );
-
- RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_336_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_336_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_336_OFFSET ,0xF80FFFFFU ,0x08000004U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_337 @ 0XFF981544</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_337_PERMISSION 0x40
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_337_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_337_PARITY 0x0
-
- Entry 337 of the Aperture Permission List, for 32-byte IPI buffer 081 at BASE_32B + 0x00000A20
- (OFFSET, MASK, VALUE) (0XFF981544, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_337_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_337_PARITY_MASK | 0 );
-
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_337_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_337_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_337_OFFSET ,0xF80FFFFFU ,0x08000040U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_338 @ 0XFF981548</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_338_PERMISSION 0x8
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_338_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_338_PARITY 0x0
-
- Entry 338 of the Aperture Permission List, for 32-byte IPI buffer 082 at BASE_32B + 0x00000A40
- (OFFSET, MASK, VALUE) (0XFF981548, 0xF80FFFFFU ,0x08000008U)
- RegMask = (LPD_XPPU_CFG_APERPERM_338_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_338_PARITY_MASK | 0 );
-
- RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_338_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_338_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_338_OFFSET ,0xF80FFFFFU ,0x08000008U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_339 @ 0XFF98154C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_339_PERMISSION 0x80
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_339_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_339_PARITY 0x0
-
- Entry 339 of the Aperture Permission List, for 32-byte IPI buffer 083 at BASE_32B + 0x00000A60
- (OFFSET, MASK, VALUE) (0XFF98154C, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_339_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_339_PARITY_MASK | 0 );
-
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_339_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_339_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_339_OFFSET ,0xF80FFFFFU ,0x08000080U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_340 @ 0XFF981550</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_340_PERMISSION 0x1
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_340_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_340_PARITY 0x0
-
- Entry 340 of the Aperture Permission List, for 32-byte IPI buffer 084 at BASE_32B + 0x00000A80
- (OFFSET, MASK, VALUE) (0XFF981550, 0xF80FFFFFU ,0x08000001U)
- RegMask = (LPD_XPPU_CFG_APERPERM_340_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_340_PARITY_MASK | 0 );
-
- RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_340_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_340_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_340_OFFSET ,0xF80FFFFFU ,0x08000001U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_341 @ 0XFF981554</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_341_PERMISSION 0x10
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_341_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_341_PARITY 0x0
-
- Entry 341 of the Aperture Permission List, for 32-byte IPI buffer 085 at BASE_32B + 0x00000AA0
- (OFFSET, MASK, VALUE) (0XFF981554, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_341_PARITY_MASK | 0 );
-
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_341_OFFSET ,0xF80FFFFFU ,0x08000010U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_342 @ 0XFF981558</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_342_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_342_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_342_PARITY 0x0
-
- Entry 342 of the Aperture Permission List, for 32-byte IPI buffer 086 at BASE_32B + 0x00000AC0
- (OFFSET, MASK, VALUE) (0XFF981558, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_342_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_342_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_342_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_342_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_342_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_342_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_342_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_343 @ 0XFF98155C</p>
-
- This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.
- PSU_LPD_XPPU_CFG_APERPERM_343_PERMISSION 0x80000
-
- 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_343_TRUSTZONE 0x1
-
- SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_343_PARITY 0x0
-
- Entry 343 of the Aperture Permission List, for 32-byte IPI buffer 087 at BASE_32B + 0x00000AE0
- (OFFSET, MASK, VALUE) (0XFF98155C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_343_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_343_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_343_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_343_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_343_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_343_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_343_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_051_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
// : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_344 @ 0XFF981560</p>
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
+ // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
+ // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
+ // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
+ // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
+ // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
+ // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
+ // : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
+ // : APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40FFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
+ // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
+ // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
+ // : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
+ // : APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF
+ // : APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97FFFF
+ // : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
+ // : APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF
+ // : APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF
+ // : APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9CFFFF
+ // : APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF
+ // : APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF
+ // : APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FFFFF
+ // : APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF
+ // : APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF
+ // : APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2FFFF
+ // : APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FFFF
+ // : APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4FFFF
+ // : APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF
+ // : APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF
+ // : APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7FFFF
+ // : APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF
+ // : APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF
+ // : APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF
+ // : APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF
+ // : APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF
+ // : APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF
+ // : APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF
+ // : APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
+ // : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
+ // : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
+ // : APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF
+ // : APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF
+ // : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
+ // : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
+ // : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF
+ // : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF
+ // : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
+ // : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
+ // : APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF
+ // : APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF
+ // : APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF
+ // : APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF
+ // : APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF
+ // : APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF
+ // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
+ // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
+ // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
+ // : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
+ // : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF
+ // : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF
+ // : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
+ // : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
+ // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
+ // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
+ // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
+ // : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
+ // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
+ // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
+ // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
+ // : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
+ // : APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF
+ // : APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: FFE1FFFF
+ // : APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF
+ // : APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: FFE3FFFF
+ // : APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDRESS: FFE4FFFF
+ // : APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FFE5FFFF
+ // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
+ // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
+ // : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
+ // : APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFFF
+ // : APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEAFFFF
+ // : APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFFF
+ // : APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDRESS: FFECFFFF
+ // : APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FFEDFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
+ // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
+ // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
+ // : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_256 @ 0XFF981400</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_344_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_256_PERMISSION 0x40
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_344_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_256_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_344_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_256_PARITY 0x0
- Entry 344 of the Aperture Permission List, for 32-byte IPI buffer 088 at BASE_32B + 0x00000B00
- (OFFSET, MASK, VALUE) (0XFF981560, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_344_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_344_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_344_PARITY_MASK | 0 );
+ Entry 256 of the Aperture Permission List, for 32-byte IPI buffer 000 at BASE_32B + 0x00000000
+ (OFFSET, MASK, VALUE) (0XFF981400, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_256_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_344_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_344_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_344_PARITY_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_344_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_256_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_345 @ 0XFF981564</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_257 @ 0XFF981404</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_345_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_257_PERMISSION 0x40
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_345_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_257_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_345_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_257_PARITY 0x0
- Entry 345 of the Aperture Permission List, for 32-byte IPI buffer 089 at BASE_32B + 0x00000B20
- (OFFSET, MASK, VALUE) (0XFF981564, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_345_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_345_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_345_PARITY_MASK | 0 );
+ Entry 257 of the Aperture Permission List, for 32-byte IPI buffer 001 at BASE_32B + 0x00000020
+ (OFFSET, MASK, VALUE) (0XFF981404, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_257_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_345_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_345_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_345_PARITY_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_345_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_257_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_346 @ 0XFF981568</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_258 @ 0XFF981408</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_346_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_258_PERMISSION 0x48
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_346_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_258_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_346_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_258_PARITY 0x0
- Entry 346 of the Aperture Permission List, for 32-byte IPI buffer 090 at BASE_32B + 0x00000B40
- (OFFSET, MASK, VALUE) (0XFF981568, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_346_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_346_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_346_PARITY_MASK | 0 );
+ Entry 258 of the Aperture Permission List, for 32-byte IPI buffer 002 at BASE_32B + 0x00000040
+ (OFFSET, MASK, VALUE) (0XFF981408, 0xF80FFFFFU ,0x08000048U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_258_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_346_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_346_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_346_PARITY_SHIFT
+ RegVal = ((0x00000048U << LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_346_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_258_OFFSET ,0xF80FFFFFU ,0x08000048U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_347 @ 0XFF98156C</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_259 @ 0XFF98140C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_347_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_259_PERMISSION 0x84
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_347_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_259_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_347_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_259_PARITY 0x0
- Entry 347 of the Aperture Permission List, for 32-byte IPI buffer 091 at BASE_32B + 0x00000B60
- (OFFSET, MASK, VALUE) (0XFF98156C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_347_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_347_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_347_PARITY_MASK | 0 );
+ Entry 259 of the Aperture Permission List, for 32-byte IPI buffer 003 at BASE_32B + 0x00000060
+ (OFFSET, MASK, VALUE) (0XFF98140C, 0xF80FFFFFU ,0x08000084U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_259_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_347_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_347_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_347_PARITY_SHIFT
+ RegVal = ((0x00000084U << LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_347_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_259_OFFSET ,0xF80FFFFFU ,0x08000084U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_348 @ 0XFF981570</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_260 @ 0XFF981410</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_348_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_260_PERMISSION 0x41
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_348_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_260_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_348_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_260_PARITY 0x0
- Entry 348 of the Aperture Permission List, for 32-byte IPI buffer 092 at BASE_32B + 0x00000B80
- (OFFSET, MASK, VALUE) (0XFF981570, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_348_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_348_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_348_PARITY_MASK | 0 );
+ Entry 260 of the Aperture Permission List, for 32-byte IPI buffer 004 at BASE_32B + 0x00000080
+ (OFFSET, MASK, VALUE) (0XFF981410, 0xF80FFFFFU ,0x08000041U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_260_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_348_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_348_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_348_PARITY_SHIFT
+ RegVal = ((0x00000041U << LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_348_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_260_OFFSET ,0xF80FFFFFU ,0x08000041U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_349 @ 0XFF981574</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_261 @ 0XFF981414</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_349_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_261_PERMISSION 0x14
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_349_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_261_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_349_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_261_PARITY 0x0
- Entry 349 of the Aperture Permission List, for 32-byte IPI buffer 093 at BASE_32B + 0x00000BA0
- (OFFSET, MASK, VALUE) (0XFF981574, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_349_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_349_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_349_PARITY_MASK | 0 );
+ Entry 261 of the Aperture Permission List, for 32-byte IPI buffer 005 at BASE_32B + 0x000000A0
+ (OFFSET, MASK, VALUE) (0XFF981414, 0xF80FFFFFU ,0x08000014U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_261_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_349_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_349_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_349_PARITY_SHIFT
+ RegVal = ((0x00000014U << LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_349_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_261_OFFSET ,0xF80FFFFFU ,0x08000014U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_350 @ 0XFF981578</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_262 @ 0XFF981418</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_350_PERMISSION 0x2
+ PSU_LPD_XPPU_CFG_APERPERM_262_PERMISSION 0x40
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_350_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_262_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_350_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_262_PARITY 0x0
- Entry 350 of the Aperture Permission List, for 32-byte IPI buffer 094 at BASE_32B + 0x00000BC0
- (OFFSET, MASK, VALUE) (0XFF981578, 0xF80FFFFFU ,0x08000002U)
- RegMask = (LPD_XPPU_CFG_APERPERM_350_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_350_PARITY_MASK | 0 );
+ Entry 262 of the Aperture Permission List, for 32-byte IPI buffer 006 at BASE_32B + 0x000000C0
+ (OFFSET, MASK, VALUE) (0XFF981418, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_262_PARITY_MASK | 0 );
- RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_350_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_350_PARITY_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_350_OFFSET ,0xF80FFFFFU ,0x08000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_262_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
- /*Register : APERPERM_351 @ 0XFF98157C</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_263 @ 0XFF98141C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_351_PERMISSION 0x20
+ PSU_LPD_XPPU_CFG_APERPERM_263_PERMISSION 0x4
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_351_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_263_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_351_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_263_PARITY 0x0
- Entry 351 of the Aperture Permission List, for 32-byte IPI buffer 095 at BASE_32B + 0x00000BE0
- (OFFSET, MASK, VALUE) (0XFF98157C, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_351_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_351_PARITY_MASK | 0 );
+ Entry 263 of the Aperture Permission List, for 32-byte IPI buffer 007 at BASE_32B + 0x000000E0
+ (OFFSET, MASK, VALUE) (0XFF98141C, 0xF80FFFFFU ,0x08000004U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_263_PARITY_MASK | 0 );
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_351_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_351_PARITY_SHIFT
+ RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_351_OFFSET ,0xF80FFFFFU ,0x08000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_263_OFFSET ,0xF80FFFFFU ,0x08000004U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_352 @ 0XFF981580</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_264 @ 0XFF981420</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_352_PERMISSION 0x4
+ PSU_LPD_XPPU_CFG_APERPERM_264_PERMISSION 0x40
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_352_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_264_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_352_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_264_PARITY 0x0
- Entry 352 of the Aperture Permission List, for 32-byte IPI buffer 096 at BASE_32B + 0x00000C00
- (OFFSET, MASK, VALUE) (0XFF981580, 0xF80FFFFFU ,0x08000004U)
- RegMask = (LPD_XPPU_CFG_APERPERM_352_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_352_PARITY_MASK | 0 );
+ Entry 264 of the Aperture Permission List, for 32-byte IPI buffer 008 at BASE_32B + 0x00000100
+ (OFFSET, MASK, VALUE) (0XFF981420, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_264_PARITY_MASK | 0 );
- RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_352_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_352_PARITY_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_352_OFFSET ,0xF80FFFFFU ,0x08000004U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_264_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_353 @ 0XFF981584</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_265 @ 0XFF981424</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_353_PERMISSION 0x40
+ PSU_LPD_XPPU_CFG_APERPERM_265_PERMISSION 0x4
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_353_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_265_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_353_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_265_PARITY 0x0
- Entry 353 of the Aperture Permission List, for 32-byte IPI buffer 097 at BASE_32B + 0x00000C20
- (OFFSET, MASK, VALUE) (0XFF981584, 0xF80FFFFFU ,0x08000040U)
- RegMask = (LPD_XPPU_CFG_APERPERM_353_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_353_PARITY_MASK | 0 );
+ Entry 265 of the Aperture Permission List, for 32-byte IPI buffer 009 at BASE_32B + 0x00000120
+ (OFFSET, MASK, VALUE) (0XFF981424, 0xF80FFFFFU ,0x08000004U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_265_PARITY_MASK | 0 );
- RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_353_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_353_PARITY_SHIFT
+ RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_265_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_353_OFFSET ,0xF80FFFFFU ,0x08000040U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_265_OFFSET ,0xF80FFFFFU ,0x08000004U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_354 @ 0XFF981588</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_266 @ 0XFF981428</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_354_PERMISSION 0x8
+ PSU_LPD_XPPU_CFG_APERPERM_266_PERMISSION 0x40
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_354_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_266_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_354_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_266_PARITY 0x0
- Entry 354 of the Aperture Permission List, for 32-byte IPI buffer 098 at BASE_32B + 0x00000C40
- (OFFSET, MASK, VALUE) (0XFF981588, 0xF80FFFFFU ,0x08000008U)
- RegMask = (LPD_XPPU_CFG_APERPERM_354_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_354_PARITY_MASK | 0 );
+ Entry 266 of the Aperture Permission List, for 32-byte IPI buffer 010 at BASE_32B + 0x00000140
+ (OFFSET, MASK, VALUE) (0XFF981428, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_266_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_266_PARITY_MASK | 0 );
- RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_354_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_354_PARITY_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_266_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_266_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_266_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_354_OFFSET ,0xF80FFFFFU ,0x08000008U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_266_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_355 @ 0XFF98158C</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_267 @ 0XFF98142C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_355_PERMISSION 0x80
+ PSU_LPD_XPPU_CFG_APERPERM_267_PERMISSION 0x4
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_355_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_267_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_355_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_267_PARITY 0x0
- Entry 355 of the Aperture Permission List, for 32-byte IPI buffer 099 at BASE_32B + 0x00000C60
- (OFFSET, MASK, VALUE) (0XFF98158C, 0xF80FFFFFU ,0x08000080U)
- RegMask = (LPD_XPPU_CFG_APERPERM_355_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_355_PARITY_MASK | 0 );
+ Entry 267 of the Aperture Permission List, for 32-byte IPI buffer 011 at BASE_32B + 0x00000160
+ (OFFSET, MASK, VALUE) (0XFF98142C, 0xF80FFFFFU ,0x08000004U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_267_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_267_PARITY_MASK | 0 );
- RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_355_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_355_PARITY_SHIFT
+ RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_267_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_267_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_267_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_355_OFFSET ,0xF80FFFFFU ,0x08000080U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_267_OFFSET ,0xF80FFFFFU ,0x08000004U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_356 @ 0XFF981590</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_268 @ 0XFF981430</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_356_PERMISSION 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_268_PERMISSION 0x40
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_356_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_268_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_356_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_268_PARITY 0x0
- Entry 356 of the Aperture Permission List, for 32-byte IPI buffer 100 at BASE_32B + 0x00000C80
- (OFFSET, MASK, VALUE) (0XFF981590, 0xF80FFFFFU ,0x08000001U)
- RegMask = (LPD_XPPU_CFG_APERPERM_356_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_356_PARITY_MASK | 0 );
+ Entry 268 of the Aperture Permission List, for 32-byte IPI buffer 012 at BASE_32B + 0x00000180
+ (OFFSET, MASK, VALUE) (0XFF981430, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_268_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_268_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_356_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_356_PARITY_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_268_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_268_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_268_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_356_OFFSET ,0xF80FFFFFU ,0x08000001U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_268_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_357 @ 0XFF981594</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_269 @ 0XFF981434</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_357_PERMISSION 0x10
+ PSU_LPD_XPPU_CFG_APERPERM_269_PERMISSION 0x4
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_357_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_269_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_357_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_269_PARITY 0x0
- Entry 357 of the Aperture Permission List, for 32-byte IPI buffer 101 at BASE_32B + 0x00000CA0
- (OFFSET, MASK, VALUE) (0XFF981594, 0xF80FFFFFU ,0x08000010U)
- RegMask = (LPD_XPPU_CFG_APERPERM_357_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_357_PARITY_MASK | 0 );
+ Entry 269 of the Aperture Permission List, for 32-byte IPI buffer 013 at BASE_32B + 0x000001A0
+ (OFFSET, MASK, VALUE) (0XFF981434, 0xF80FFFFFU ,0x08000004U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_269_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_269_PARITY_MASK | 0 );
- RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_357_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_357_PARITY_SHIFT
+ RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_269_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_269_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_269_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_357_OFFSET ,0xF80FFFFFU ,0x08000010U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_269_OFFSET ,0xF80FFFFFU ,0x08000004U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_358 @ 0XFF981598</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_270 @ 0XFF981438</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_358_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_270_PERMISSION 0x42
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_358_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_270_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_358_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_270_PARITY 0x0
- Entry 358 of the Aperture Permission List, for 32-byte IPI buffer 102 at BASE_32B + 0x00000CC0
- (OFFSET, MASK, VALUE) (0XFF981598, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_358_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_358_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_358_PARITY_MASK | 0 );
+ Entry 270 of the Aperture Permission List, for 32-byte IPI buffer 014 at BASE_32B + 0x000001C0
+ (OFFSET, MASK, VALUE) (0XFF981438, 0xF80FFFFFU ,0x08000042U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_270_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_270_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_358_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_358_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_358_PARITY_SHIFT
+ RegVal = ((0x00000042U << LPD_XPPU_CFG_APERPERM_270_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_270_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_270_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_358_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_270_OFFSET ,0xF80FFFFFU ,0x08000042U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_359 @ 0XFF98159C</p>
+ // : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
+ /*Register : APERPERM_271 @ 0XFF98143C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_359_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_271_PERMISSION 0x24
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_359_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_271_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_359_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_271_PARITY 0x0
- Entry 359 of the Aperture Permission List, for 32-byte IPI buffer 103 at BASE_32B + 0x00000CE0
- (OFFSET, MASK, VALUE) (0XFF98159C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_359_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_359_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_359_PARITY_MASK | 0 );
+ Entry 271 of the Aperture Permission List, for 32-byte IPI buffer 015 at BASE_32B + 0x000001E0
+ (OFFSET, MASK, VALUE) (0XFF98143C, 0xF80FFFFFU ,0x08000024U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_271_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_271_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_359_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_359_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_359_PARITY_SHIFT
+ RegVal = ((0x00000024U << LPD_XPPU_CFG_APERPERM_271_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_271_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_271_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_359_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_271_OFFSET ,0xF80FFFFFU ,0x08000024U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_360 @ 0XFF9815A0</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_272 @ 0XFF981440</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_360_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_272_PERMISSION 0x84
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_360_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_272_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_360_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_272_PARITY 0x0
- Entry 360 of the Aperture Permission List, for 32-byte IPI buffer 104 at BASE_32B + 0x00000D00
- (OFFSET, MASK, VALUE) (0XFF9815A0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_360_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_360_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_360_PARITY_MASK | 0 );
+ Entry 272 of the Aperture Permission List, for 32-byte IPI buffer 016 at BASE_32B + 0x00000200
+ (OFFSET, MASK, VALUE) (0XFF981440, 0xF80FFFFFU ,0x08000084U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_272_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_272_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_360_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_360_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_360_PARITY_SHIFT
+ RegVal = ((0x00000084U << LPD_XPPU_CFG_APERPERM_272_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_272_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_272_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_360_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_272_OFFSET ,0xF80FFFFFU ,0x08000084U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_361 @ 0XFF9815A4</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_273 @ 0XFF981444</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_361_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_273_PERMISSION 0x48
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_361_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_273_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_361_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_273_PARITY 0x0
- Entry 361 of the Aperture Permission List, for 32-byte IPI buffer 105 at BASE_32B + 0x00000D20
- (OFFSET, MASK, VALUE) (0XFF9815A4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_361_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_361_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_361_PARITY_MASK | 0 );
+ Entry 273 of the Aperture Permission List, for 32-byte IPI buffer 017 at BASE_32B + 0x00000220
+ (OFFSET, MASK, VALUE) (0XFF981444, 0xF80FFFFFU ,0x08000048U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_273_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_273_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_361_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_361_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_361_PARITY_SHIFT
+ RegVal = ((0x00000048U << LPD_XPPU_CFG_APERPERM_273_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_273_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_273_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_361_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_273_OFFSET ,0xF80FFFFFU ,0x08000048U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_362 @ 0XFF9815A8</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_274 @ 0XFF981448</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_362_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_274_PERMISSION 0x80
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_362_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_274_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_362_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_274_PARITY 0x0
- Entry 362 of the Aperture Permission List, for 32-byte IPI buffer 106 at BASE_32B + 0x00000D40
- (OFFSET, MASK, VALUE) (0XFF9815A8, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_362_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_362_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_362_PARITY_MASK | 0 );
+ Entry 274 of the Aperture Permission List, for 32-byte IPI buffer 018 at BASE_32B + 0x00000240
+ (OFFSET, MASK, VALUE) (0XFF981448, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_274_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_274_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_362_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_362_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_362_PARITY_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_274_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_274_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_274_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_362_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_274_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_363 @ 0XFF9815AC</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_275 @ 0XFF98144C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_363_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_275_PERMISSION 0x80
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_363_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_275_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_363_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_275_PARITY 0x0
- Entry 363 of the Aperture Permission List, for 32-byte IPI buffer 107 at BASE_32B + 0x00000D60
- (OFFSET, MASK, VALUE) (0XFF9815AC, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_363_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_363_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_363_PARITY_MASK | 0 );
+ Entry 275 of the Aperture Permission List, for 32-byte IPI buffer 019 at BASE_32B + 0x00000260
+ (OFFSET, MASK, VALUE) (0XFF98144C, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_275_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_275_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_363_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_363_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_363_PARITY_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_275_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_275_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_275_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_363_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_275_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_364 @ 0XFF9815B0</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_276 @ 0XFF981450</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_364_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_276_PERMISSION 0x81
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_364_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_276_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_364_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_276_PARITY 0x0
- Entry 364 of the Aperture Permission List, for 32-byte IPI buffer 108 at BASE_32B + 0x00000D80
- (OFFSET, MASK, VALUE) (0XFF9815B0, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_364_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_364_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_364_PARITY_MASK | 0 );
+ Entry 276 of the Aperture Permission List, for 32-byte IPI buffer 020 at BASE_32B + 0x00000280
+ (OFFSET, MASK, VALUE) (0XFF981450, 0xF80FFFFFU ,0x08000081U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_276_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_276_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_364_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_364_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_364_PARITY_SHIFT
+ RegVal = ((0x00000081U << LPD_XPPU_CFG_APERPERM_276_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_276_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_276_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_364_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_276_OFFSET ,0xF80FFFFFU ,0x08000081U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_365 @ 0XFF9815B4</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_277 @ 0XFF981454</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_365_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_277_PERMISSION 0x18
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_365_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_277_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_365_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_277_PARITY 0x0
- Entry 365 of the Aperture Permission List, for 32-byte IPI buffer 109 at BASE_32B + 0x00000DA0
- (OFFSET, MASK, VALUE) (0XFF9815B4, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_365_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_365_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_365_PARITY_MASK | 0 );
+ Entry 277 of the Aperture Permission List, for 32-byte IPI buffer 021 at BASE_32B + 0x000002A0
+ (OFFSET, MASK, VALUE) (0XFF981454, 0xF80FFFFFU ,0x08000018U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_277_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_277_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_365_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_365_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_365_PARITY_SHIFT
+ RegVal = ((0x00000018U << LPD_XPPU_CFG_APERPERM_277_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_277_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_277_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_365_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_277_OFFSET ,0xF80FFFFFU ,0x08000018U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_366 @ 0XFF9815B8</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_278 @ 0XFF981458</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_366_PERMISSION 0x2
+ PSU_LPD_XPPU_CFG_APERPERM_278_PERMISSION 0x80
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_366_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_278_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_366_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_278_PARITY 0x0
- Entry 366 of the Aperture Permission List, for 32-byte IPI buffer 110 at BASE_32B + 0x00000DC0
- (OFFSET, MASK, VALUE) (0XFF9815B8, 0xF80FFFFFU ,0x08000002U)
- RegMask = (LPD_XPPU_CFG_APERPERM_366_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_366_PARITY_MASK | 0 );
+ Entry 278 of the Aperture Permission List, for 32-byte IPI buffer 022 at BASE_32B + 0x000002C0
+ (OFFSET, MASK, VALUE) (0XFF981458, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_278_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_278_PARITY_MASK | 0 );
- RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_366_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_366_PARITY_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_278_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_278_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_278_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_366_OFFSET ,0xF80FFFFFU ,0x08000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_278_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
- /*Register : APERPERM_367 @ 0XFF9815BC</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_279 @ 0XFF98145C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_367_PERMISSION 0x20
+ PSU_LPD_XPPU_CFG_APERPERM_279_PERMISSION 0x8
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_367_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_279_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_367_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_279_PARITY 0x0
- Entry 367 of the Aperture Permission List, for 32-byte IPI buffer 111 at BASE_32B + 0x00000DE0
- (OFFSET, MASK, VALUE) (0XFF9815BC, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_367_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_367_PARITY_MASK | 0 );
+ Entry 279 of the Aperture Permission List, for 32-byte IPI buffer 023 at BASE_32B + 0x000002E0
+ (OFFSET, MASK, VALUE) (0XFF98145C, 0xF80FFFFFU ,0x08000008U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_279_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_279_PARITY_MASK | 0 );
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_367_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_367_PARITY_SHIFT
+ RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_279_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_279_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_279_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_367_OFFSET ,0xF80FFFFFU ,0x08000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_279_OFFSET ,0xF80FFFFFU ,0x08000008U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_368 @ 0XFF9815C0</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_280 @ 0XFF981460</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_368_PERMISSION 0x24
+ PSU_LPD_XPPU_CFG_APERPERM_280_PERMISSION 0x80
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_368_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_280_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_368_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_280_PARITY 0x0
- Entry 368 of the Aperture Permission List, for 32-byte IPI buffer 112 at BASE_32B + 0x00000E00
- (OFFSET, MASK, VALUE) (0XFF9815C0, 0xF80FFFFFU ,0x08000024U)
- RegMask = (LPD_XPPU_CFG_APERPERM_368_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_368_PARITY_MASK | 0 );
+ Entry 280 of the Aperture Permission List, for 32-byte IPI buffer 024 at BASE_32B + 0x00000300
+ (OFFSET, MASK, VALUE) (0XFF981460, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_280_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_280_PARITY_MASK | 0 );
- RegVal = ((0x00000024U << LPD_XPPU_CFG_APERPERM_368_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_368_PARITY_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_280_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_280_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_280_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_368_OFFSET ,0xF80FFFFFU ,0x08000024U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_280_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_369 @ 0XFF9815C4</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_281 @ 0XFF981464</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_369_PERMISSION 0x42
+ PSU_LPD_XPPU_CFG_APERPERM_281_PERMISSION 0x8
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_369_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_281_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_369_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_281_PARITY 0x0
- Entry 369 of the Aperture Permission List, for 32-byte IPI buffer 113 at BASE_32B + 0x00000E20
- (OFFSET, MASK, VALUE) (0XFF9815C4, 0xF80FFFFFU ,0x08000042U)
- RegMask = (LPD_XPPU_CFG_APERPERM_369_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_369_PARITY_MASK | 0 );
+ Entry 281 of the Aperture Permission List, for 32-byte IPI buffer 025 at BASE_32B + 0x00000320
+ (OFFSET, MASK, VALUE) (0XFF981464, 0xF80FFFFFU ,0x08000008U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_281_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_281_PARITY_MASK | 0 );
- RegVal = ((0x00000042U << LPD_XPPU_CFG_APERPERM_369_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_369_PARITY_SHIFT
+ RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_281_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_281_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_281_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_369_OFFSET ,0xF80FFFFFU ,0x08000042U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_281_OFFSET ,0xF80FFFFFU ,0x08000008U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_370 @ 0XFF9815C8</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_282 @ 0XFF981468</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_370_PERMISSION 0x28
+ PSU_LPD_XPPU_CFG_APERPERM_282_PERMISSION 0x80
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_370_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_282_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_370_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_282_PARITY 0x0
- Entry 370 of the Aperture Permission List, for 32-byte IPI buffer 114 at BASE_32B + 0x00000E40
- (OFFSET, MASK, VALUE) (0XFF9815C8, 0xF80FFFFFU ,0x08000028U)
- RegMask = (LPD_XPPU_CFG_APERPERM_370_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_370_PARITY_MASK | 0 );
+ Entry 282 of the Aperture Permission List, for 32-byte IPI buffer 026 at BASE_32B + 0x00000340
+ (OFFSET, MASK, VALUE) (0XFF981468, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_282_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_282_PARITY_MASK | 0 );
- RegVal = ((0x00000028U << LPD_XPPU_CFG_APERPERM_370_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_370_PARITY_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_282_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_282_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_282_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_370_OFFSET ,0xF80FFFFFU ,0x08000028U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_282_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_371 @ 0XFF9815CC</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_283 @ 0XFF98146C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_371_PERMISSION 0x82
+ PSU_LPD_XPPU_CFG_APERPERM_283_PERMISSION 0x8
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_371_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_283_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_371_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_283_PARITY 0x0
- Entry 371 of the Aperture Permission List, for 32-byte IPI buffer 115 at BASE_32B + 0x00000E60
- (OFFSET, MASK, VALUE) (0XFF9815CC, 0xF80FFFFFU ,0x08000082U)
- RegMask = (LPD_XPPU_CFG_APERPERM_371_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_371_PARITY_MASK | 0 );
+ Entry 283 of the Aperture Permission List, for 32-byte IPI buffer 027 at BASE_32B + 0x00000360
+ (OFFSET, MASK, VALUE) (0XFF98146C, 0xF80FFFFFU ,0x08000008U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_283_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_283_PARITY_MASK | 0 );
- RegVal = ((0x00000082U << LPD_XPPU_CFG_APERPERM_371_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_371_PARITY_SHIFT
+ RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_283_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_283_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_283_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_371_OFFSET ,0xF80FFFFFU ,0x08000082U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_283_OFFSET ,0xF80FFFFFU ,0x08000008U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_372 @ 0XFF9815D0</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_284 @ 0XFF981470</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_372_PERMISSION 0x21
+ PSU_LPD_XPPU_CFG_APERPERM_284_PERMISSION 0x80
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_372_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_284_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_372_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_284_PARITY 0x0
- Entry 372 of the Aperture Permission List, for 32-byte IPI buffer 116 at BASE_32B + 0x00000E80
- (OFFSET, MASK, VALUE) (0XFF9815D0, 0xF80FFFFFU ,0x08000021U)
- RegMask = (LPD_XPPU_CFG_APERPERM_372_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_372_PARITY_MASK | 0 );
+ Entry 284 of the Aperture Permission List, for 32-byte IPI buffer 028 at BASE_32B + 0x00000380
+ (OFFSET, MASK, VALUE) (0XFF981470, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_284_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_284_PARITY_MASK | 0 );
- RegVal = ((0x00000021U << LPD_XPPU_CFG_APERPERM_372_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_372_PARITY_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_284_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_284_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_284_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_372_OFFSET ,0xF80FFFFFU ,0x08000021U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_284_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_373 @ 0XFF9815D4</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_285 @ 0XFF981474</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_373_PERMISSION 0x12
+ PSU_LPD_XPPU_CFG_APERPERM_285_PERMISSION 0x8
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_373_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_285_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_373_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_285_PARITY 0x0
- Entry 373 of the Aperture Permission List, for 32-byte IPI buffer 117 at BASE_32B + 0x00000EA0
- (OFFSET, MASK, VALUE) (0XFF9815D4, 0xF80FFFFFU ,0x08000012U)
- RegMask = (LPD_XPPU_CFG_APERPERM_373_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_373_PARITY_MASK | 0 );
+ Entry 285 of the Aperture Permission List, for 32-byte IPI buffer 029 at BASE_32B + 0x000003A0
+ (OFFSET, MASK, VALUE) (0XFF981474, 0xF80FFFFFU ,0x08000008U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_285_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_285_PARITY_MASK | 0 );
- RegVal = ((0x00000012U << LPD_XPPU_CFG_APERPERM_373_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_373_PARITY_SHIFT
+ RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_285_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_285_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_285_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_373_OFFSET ,0xF80FFFFFU ,0x08000012U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_285_OFFSET ,0xF80FFFFFU ,0x08000008U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_374 @ 0XFF9815D8</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_286 @ 0XFF981478</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_374_PERMISSION 0x20
+ PSU_LPD_XPPU_CFG_APERPERM_286_PERMISSION 0x82
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_374_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_286_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_374_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_286_PARITY 0x0
- Entry 374 of the Aperture Permission List, for 32-byte IPI buffer 118 at BASE_32B + 0x00000EC0
- (OFFSET, MASK, VALUE) (0XFF9815D8, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_374_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_374_PARITY_MASK | 0 );
+ Entry 286 of the Aperture Permission List, for 32-byte IPI buffer 030 at BASE_32B + 0x000003C0
+ (OFFSET, MASK, VALUE) (0XFF981478, 0xF80FFFFFU ,0x08000082U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_286_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_286_PARITY_MASK | 0 );
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_374_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_374_PARITY_SHIFT
+ RegVal = ((0x00000082U << LPD_XPPU_CFG_APERPERM_286_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_286_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_286_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_374_OFFSET ,0xF80FFFFFU ,0x08000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_286_OFFSET ,0xF80FFFFFU ,0x08000082U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_375 @ 0XFF9815DC</p>
+ // : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
+ /*Register : APERPERM_287 @ 0XFF98147C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_375_PERMISSION 0x2
+ PSU_LPD_XPPU_CFG_APERPERM_287_PERMISSION 0x28
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_375_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_287_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_375_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_287_PARITY 0x0
- Entry 375 of the Aperture Permission List, for 32-byte IPI buffer 119 at BASE_32B + 0x00000EE0
- (OFFSET, MASK, VALUE) (0XFF9815DC, 0xF80FFFFFU ,0x08000002U)
- RegMask = (LPD_XPPU_CFG_APERPERM_375_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_375_PARITY_MASK | 0 );
+ Entry 287 of the Aperture Permission List, for 32-byte IPI buffer 031 at BASE_32B + 0x000003E0
+ (OFFSET, MASK, VALUE) (0XFF98147C, 0xF80FFFFFU ,0x08000028U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_287_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_287_PARITY_MASK | 0 );
- RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_375_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_375_PARITY_SHIFT
+ RegVal = ((0x00000028U << LPD_XPPU_CFG_APERPERM_287_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_287_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_287_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_375_OFFSET ,0xF80FFFFFU ,0x08000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_287_OFFSET ,0xF80FFFFFU ,0x08000028U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_376 @ 0XFF9815E0</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_288 @ 0XFF981480</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_376_PERMISSION 0x20
+ PSU_LPD_XPPU_CFG_APERPERM_288_PERMISSION 0x14
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_376_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_288_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_376_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_288_PARITY 0x0
- Entry 376 of the Aperture Permission List, for 32-byte IPI buffer 120 at BASE_32B + 0x00000F00
- (OFFSET, MASK, VALUE) (0XFF9815E0, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_376_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_376_PARITY_MASK | 0 );
+ Entry 288 of the Aperture Permission List, for 32-byte IPI buffer 032 at BASE_32B + 0x00000400
+ (OFFSET, MASK, VALUE) (0XFF981480, 0xF80FFFFFU ,0x08000014U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_288_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_288_PARITY_MASK | 0 );
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_376_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_376_PARITY_SHIFT
+ RegVal = ((0x00000014U << LPD_XPPU_CFG_APERPERM_288_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_288_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_288_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_376_OFFSET ,0xF80FFFFFU ,0x08000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_288_OFFSET ,0xF80FFFFFU ,0x08000014U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_377 @ 0XFF9815E4</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_289 @ 0XFF981484</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_377_PERMISSION 0x2
+ PSU_LPD_XPPU_CFG_APERPERM_289_PERMISSION 0x41
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_377_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_289_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_377_PARITY 0x0
-
- Entry 377 of the Aperture Permission List, for 32-byte IPI buffer 121 at BASE_32B + 0x00000F20
- (OFFSET, MASK, VALUE) (0XFF9815E4, 0xF80FFFFFU ,0x08000002U)
- RegMask = (LPD_XPPU_CFG_APERPERM_377_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_377_PARITY_MASK | 0 );
+ PSU_LPD_XPPU_CFG_APERPERM_289_PARITY 0x0
- RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_377_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_377_PARITY_SHIFT
+ Entry 289 of the Aperture Permission List, for 32-byte IPI buffer 033 at BASE_32B + 0x00000420
+ (OFFSET, MASK, VALUE) (0XFF981484, 0xF80FFFFFU ,0x08000041U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_289_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_289_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000041U << LPD_XPPU_CFG_APERPERM_289_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_289_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_289_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_377_OFFSET ,0xF80FFFFFU ,0x08000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_289_OFFSET ,0xF80FFFFFU ,0x08000041U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_378 @ 0XFF9815E8</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_290 @ 0XFF981488</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_378_PERMISSION 0x20
+ PSU_LPD_XPPU_CFG_APERPERM_290_PERMISSION 0x18
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_378_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_290_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_378_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_290_PARITY 0x0
- Entry 378 of the Aperture Permission List, for 32-byte IPI buffer 122 at BASE_32B + 0x00000F40
- (OFFSET, MASK, VALUE) (0XFF9815E8, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_378_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_378_PARITY_MASK | 0 );
+ Entry 290 of the Aperture Permission List, for 32-byte IPI buffer 034 at BASE_32B + 0x00000440
+ (OFFSET, MASK, VALUE) (0XFF981488, 0xF80FFFFFU ,0x08000018U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_290_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_290_PARITY_MASK | 0 );
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_378_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_378_PARITY_SHIFT
+ RegVal = ((0x00000018U << LPD_XPPU_CFG_APERPERM_290_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_290_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_290_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_378_OFFSET ,0xF80FFFFFU ,0x08000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_290_OFFSET ,0xF80FFFFFU ,0x08000018U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_379 @ 0XFF9815EC</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_291 @ 0XFF98148C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_379_PERMISSION 0x2
+ PSU_LPD_XPPU_CFG_APERPERM_291_PERMISSION 0x81
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_379_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_291_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_379_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_291_PARITY 0x0
- Entry 379 of the Aperture Permission List, for 32-byte IPI buffer 123 at BASE_32B + 0x00000F60
- (OFFSET, MASK, VALUE) (0XFF9815EC, 0xF80FFFFFU ,0x08000002U)
- RegMask = (LPD_XPPU_CFG_APERPERM_379_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_379_PARITY_MASK | 0 );
+ Entry 291 of the Aperture Permission List, for 32-byte IPI buffer 035 at BASE_32B + 0x00000460
+ (OFFSET, MASK, VALUE) (0XFF98148C, 0xF80FFFFFU ,0x08000081U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_291_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_291_PARITY_MASK | 0 );
- RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_379_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_379_PARITY_SHIFT
+ RegVal = ((0x00000081U << LPD_XPPU_CFG_APERPERM_291_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_291_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_291_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_379_OFFSET ,0xF80FFFFFU ,0x08000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_291_OFFSET ,0xF80FFFFFU ,0x08000081U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_380 @ 0XFF9815F0</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_292 @ 0XFF981490</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_380_PERMISSION 0x20
+ PSU_LPD_XPPU_CFG_APERPERM_292_PERMISSION 0x10
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_380_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_292_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_380_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_292_PARITY 0x0
- Entry 380 of the Aperture Permission List, for 32-byte IPI buffer 124 at BASE_32B + 0x00000F80
- (OFFSET, MASK, VALUE) (0XFF9815F0, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_380_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_380_PARITY_MASK | 0 );
+ Entry 292 of the Aperture Permission List, for 32-byte IPI buffer 036 at BASE_32B + 0x00000480
+ (OFFSET, MASK, VALUE) (0XFF981490, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_292_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_292_PARITY_MASK | 0 );
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_380_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_380_PARITY_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_292_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_292_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_292_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_380_OFFSET ,0xF80FFFFFU ,0x08000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_292_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_381 @ 0XFF9815F4</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_293 @ 0XFF981494</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_381_PERMISSION 0x2
+ PSU_LPD_XPPU_CFG_APERPERM_293_PERMISSION 0x10
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_381_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_293_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_381_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_293_PARITY 0x0
- Entry 381 of the Aperture Permission List, for 32-byte IPI buffer 125 at BASE_32B + 0x00000FA0
- (OFFSET, MASK, VALUE) (0XFF9815F4, 0xF80FFFFFU ,0x08000002U)
- RegMask = (LPD_XPPU_CFG_APERPERM_381_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_381_PARITY_MASK | 0 );
+ Entry 293 of the Aperture Permission List, for 32-byte IPI buffer 037 at BASE_32B + 0x000004A0
+ (OFFSET, MASK, VALUE) (0XFF981494, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_293_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_293_PARITY_MASK | 0 );
- RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_381_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_381_PARITY_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_293_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_293_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_293_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_381_OFFSET ,0xF80FFFFFU ,0x08000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_293_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_382 @ 0XFF9815F8</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_294 @ 0XFF981498</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_382_PERMISSION 0x20
+ PSU_LPD_XPPU_CFG_APERPERM_294_PERMISSION 0x10
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_382_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_294_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_382_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_294_PARITY 0x0
- Entry 382 of the Aperture Permission List, for 32-byte IPI buffer 126 at BASE_32B + 0x00000FC0
- (OFFSET, MASK, VALUE) (0XFF9815F8, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_382_PARITY_MASK | 0 );
+ Entry 294 of the Aperture Permission List, for 32-byte IPI buffer 038 at BASE_32B + 0x000004C0
+ (OFFSET, MASK, VALUE) (0XFF981498, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_294_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_294_PARITY_MASK | 0 );
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_294_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_294_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_294_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_382_OFFSET ,0xF80FFFFFU ,0x08000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_294_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
- /*Register : APERPERM_383 @ 0XFF9815FC</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_295 @ 0XFF98149C</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_383_PERMISSION 0x20
+ PSU_LPD_XPPU_CFG_APERPERM_295_PERMISSION 0x1
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_383_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_295_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_383_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_295_PARITY 0x0
- Entry 383 of the Aperture Permission List, for 32-byte IPI buffer 127 at BASE_32B + 0x00000FE0
- (OFFSET, MASK, VALUE) (0XFF9815FC, 0xF80FFFFFU ,0x08000020U)
- RegMask = (LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_383_PARITY_MASK | 0 );
+ Entry 295 of the Aperture Permission List, for 32-byte IPI buffer 039 at BASE_32B + 0x000004E0
+ (OFFSET, MASK, VALUE) (0XFF98149C, 0xF80FFFFFU ,0x08000001U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_295_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_295_PARITY_MASK | 0 );
- RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_295_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_295_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_295_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_383_OFFSET ,0xF80FFFFFU ,0x08000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_295_OFFSET ,0xF80FFFFFU ,0x08000001U);
/*############################################################################################################################ */
- // : APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF
- /*Register : APERPERM_384 @ 0XFF981600</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_296 @ 0XFF9814A0</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_384_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_296_PERMISSION 0x10
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_384_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_296_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_384_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_296_PARITY 0x0
- Entry 384 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00000000
- (OFFSET, MASK, VALUE) (0XFF981600, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_384_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_384_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_384_PARITY_MASK | 0 );
+ Entry 296 of the Aperture Permission List, for 32-byte IPI buffer 040 at BASE_32B + 0x00000500
+ (OFFSET, MASK, VALUE) (0XFF9814A0, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_296_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_296_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_384_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_384_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_384_PARITY_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_296_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_296_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_296_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_384_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_296_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- // : APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF
- /*Register : APERPERM_385 @ 0XFF981604</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_297 @ 0XFF9814A4</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_385_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_297_PERMISSION 0x1
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_385_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_297_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_385_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_297_PARITY 0x0
- Entry 385 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00100000
- (OFFSET, MASK, VALUE) (0XFF981604, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_385_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_385_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_385_PARITY_MASK | 0 );
+ Entry 297 of the Aperture Permission List, for 32-byte IPI buffer 041 at BASE_32B + 0x00000520
+ (OFFSET, MASK, VALUE) (0XFF9814A4, 0xF80FFFFFU ,0x08000001U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_297_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_297_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_385_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_385_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_385_PARITY_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_297_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_297_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_297_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_385_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_297_OFFSET ,0xF80FFFFFU ,0x08000001U);
/*############################################################################################################################ */
- // : APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFFFF
- /*Register : APERPERM_386 @ 0XFF981608</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_298 @ 0XFF9814A8</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_386_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_298_PERMISSION 0x10
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_386_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_298_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_386_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_298_PARITY 0x0
- Entry 386 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00200000
- (OFFSET, MASK, VALUE) (0XFF981608, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_386_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_386_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_386_PARITY_MASK | 0 );
+ Entry 298 of the Aperture Permission List, for 32-byte IPI buffer 042 at BASE_32B + 0x00000540
+ (OFFSET, MASK, VALUE) (0XFF9814A8, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_298_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_298_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_386_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_386_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_386_PARITY_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_298_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_298_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_298_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_386_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_298_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- // : APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFFFF
- /*Register : APERPERM_387 @ 0XFF98160C</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_299 @ 0XFF9814AC</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_387_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_299_PERMISSION 0x1
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_387_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_299_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_387_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_299_PARITY 0x0
- Entry 387 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00300000
- (OFFSET, MASK, VALUE) (0XFF98160C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_387_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_387_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_387_PARITY_MASK | 0 );
+ Entry 299 of the Aperture Permission List, for 32-byte IPI buffer 043 at BASE_32B + 0x00000560
+ (OFFSET, MASK, VALUE) (0XFF9814AC, 0xF80FFFFFU ,0x08000001U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_299_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_299_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_387_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_387_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_387_PARITY_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_299_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_299_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_299_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_387_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_299_OFFSET ,0xF80FFFFFU ,0x08000001U);
/*############################################################################################################################ */
- // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
- /*Register : APERPERM_388 @ 0XFF981610</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_300 @ 0XFF9814B0</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_388_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_300_PERMISSION 0x10
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_388_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_300_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_388_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_300_PARITY 0x0
- Entry 388 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00400000
- (OFFSET, MASK, VALUE) (0XFF981610, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_388_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_388_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_388_PARITY_MASK | 0 );
+ Entry 300 of the Aperture Permission List, for 32-byte IPI buffer 044 at BASE_32B + 0x00000580
+ (OFFSET, MASK, VALUE) (0XFF9814B0, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_300_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_300_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_388_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_388_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_388_PARITY_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_300_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_300_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_300_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_388_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_300_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
- /*Register : APERPERM_389 @ 0XFF981614</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_301 @ 0XFF9814B4</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_389_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_301_PERMISSION 0x1
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_389_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_301_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_389_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_301_PARITY 0x0
- Entry 389 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00500000
- (OFFSET, MASK, VALUE) (0XFF981614, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_389_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_389_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_389_PARITY_MASK | 0 );
+ Entry 301 of the Aperture Permission List, for 32-byte IPI buffer 045 at BASE_32B + 0x000005A0
+ (OFFSET, MASK, VALUE) (0XFF9814B4, 0xF80FFFFFU ,0x08000001U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_301_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_301_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_389_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_389_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_389_PARITY_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_301_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_301_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_301_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_389_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_301_OFFSET ,0xF80FFFFFU ,0x08000001U);
/*############################################################################################################################ */
- // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
- /*Register : APERPERM_390 @ 0XFF981618</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_302 @ 0XFF9814B8</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_390_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_302_PERMISSION 0x12
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_390_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_302_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_390_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_302_PARITY 0x0
- Entry 390 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00600000
- (OFFSET, MASK, VALUE) (0XFF981618, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_390_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_390_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_390_PARITY_MASK | 0 );
+ Entry 302 of the Aperture Permission List, for 32-byte IPI buffer 046 at BASE_32B + 0x000005C0
+ (OFFSET, MASK, VALUE) (0XFF9814B8, 0xF80FFFFFU ,0x08000012U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_302_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_302_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_390_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_390_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_390_PARITY_SHIFT
+ RegVal = ((0x00000012U << LPD_XPPU_CFG_APERPERM_302_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_302_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_302_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_390_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_302_OFFSET ,0xF80FFFFFU ,0x08000012U);
/*############################################################################################################################ */
- // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
- /*Register : APERPERM_391 @ 0XFF98161C</p>
+ // : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
+ /*Register : APERPERM_303 @ 0XFF9814BC</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_391_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_303_PERMISSION 0x21
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_391_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_303_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_391_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_303_PARITY 0x0
- Entry 391 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00700000
- (OFFSET, MASK, VALUE) (0XFF98161C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_391_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_391_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_391_PARITY_MASK | 0 );
+ Entry 303 of the Aperture Permission List, for 32-byte IPI buffer 047 at BASE_32B + 0x000005E0
+ (OFFSET, MASK, VALUE) (0XFF9814BC, 0xF80FFFFFU ,0x08000021U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_303_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_303_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_391_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_391_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_391_PARITY_SHIFT
+ RegVal = ((0x00000021U << LPD_XPPU_CFG_APERPERM_303_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_303_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_303_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_391_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_303_OFFSET ,0xF80FFFFFU ,0x08000021U);
/*############################################################################################################################ */
- // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
- /*Register : APERPERM_392 @ 0XFF981620</p>
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ /*Register : APERPERM_304 @ 0XFF9814C0</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_392_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_304_PERMISSION 0x4
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_392_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_304_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_392_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_304_PARITY 0x0
- Entry 392 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00800000
- (OFFSET, MASK, VALUE) (0XFF981620, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_392_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_392_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_392_PARITY_MASK | 0 );
+ Entry 304 of the Aperture Permission List, for 32-byte IPI buffer 048 at BASE_32B + 0x00000600
+ (OFFSET, MASK, VALUE) (0XFF9814C0, 0xF80FFFFFU ,0x08000004U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_304_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_304_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_392_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_392_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_392_PARITY_SHIFT
+ RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_304_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_304_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_304_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_392_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_304_OFFSET ,0xF80FFFFFU ,0x08000004U);
/*############################################################################################################################ */
- // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
- /*Register : APERPERM_393 @ 0XFF981624</p>
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ /*Register : APERPERM_305 @ 0XFF9814C4</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_393_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_305_PERMISSION 0x40
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_393_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_305_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_393_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_305_PARITY 0x0
- Entry 393 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00900000
- (OFFSET, MASK, VALUE) (0XFF981624, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_393_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_393_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_393_PARITY_MASK | 0 );
+ Entry 305 of the Aperture Permission List, for 32-byte IPI buffer 049 at BASE_32B + 0x00000620
+ (OFFSET, MASK, VALUE) (0XFF9814C4, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_305_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_305_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_393_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_393_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_393_PARITY_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_305_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_305_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_305_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_393_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_305_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
- /*Register : APERPERM_394 @ 0XFF981628</p>
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ /*Register : APERPERM_306 @ 0XFF9814C8</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_394_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_306_PERMISSION 0x8
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_394_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_306_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_394_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_306_PARITY 0x0
- Entry 394 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00A00000
- (OFFSET, MASK, VALUE) (0XFF981628, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_394_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_394_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_394_PARITY_MASK | 0 );
+ Entry 306 of the Aperture Permission List, for 32-byte IPI buffer 050 at BASE_32B + 0x00000640
+ (OFFSET, MASK, VALUE) (0XFF9814C8, 0xF80FFFFFU ,0x08000008U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_306_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_306_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_394_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_394_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_394_PARITY_SHIFT
+ RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_306_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_306_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_306_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_394_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_306_OFFSET ,0xF80FFFFFU ,0x08000008U);
/*############################################################################################################################ */
- // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
- /*Register : APERPERM_395 @ 0XFF98162C</p>
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ /*Register : APERPERM_307 @ 0XFF9814CC</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_395_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_307_PERMISSION 0x80
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_395_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_307_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_395_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_307_PARITY 0x0
- Entry 395 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00B00000
- (OFFSET, MASK, VALUE) (0XFF98162C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_395_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_395_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_395_PARITY_MASK | 0 );
+ Entry 307 of the Aperture Permission List, for 32-byte IPI buffer 051 at BASE_32B + 0x00000660
+ (OFFSET, MASK, VALUE) (0XFF9814CC, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_307_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_307_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_395_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_395_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_395_PARITY_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_307_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_307_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_307_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_395_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_307_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
- /*Register : APERPERM_396 @ 0XFF981630</p>
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ /*Register : APERPERM_308 @ 0XFF9814D0</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_396_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_308_PERMISSION 0x1
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_396_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_308_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_396_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_308_PARITY 0x0
- Entry 396 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00C00000
- (OFFSET, MASK, VALUE) (0XFF981630, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_396_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_396_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_396_PARITY_MASK | 0 );
+ Entry 308 of the Aperture Permission List, for 32-byte IPI buffer 052 at BASE_32B + 0x00000680
+ (OFFSET, MASK, VALUE) (0XFF9814D0, 0xF80FFFFFU ,0x08000001U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_308_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_308_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_396_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_396_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_396_PARITY_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_308_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_308_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_308_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_396_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_308_OFFSET ,0xF80FFFFFU ,0x08000001U);
/*############################################################################################################################ */
- // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
- /*Register : APERPERM_397 @ 0XFF981634</p>
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ /*Register : APERPERM_309 @ 0XFF9814D4</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_397_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_309_PERMISSION 0x10
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_397_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_309_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_397_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_309_PARITY 0x0
- Entry 397 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00D00000
- (OFFSET, MASK, VALUE) (0XFF981634, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_397_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_397_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_397_PARITY_MASK | 0 );
+ Entry 309 of the Aperture Permission List, for 32-byte IPI buffer 053 at BASE_32B + 0x000006A0
+ (OFFSET, MASK, VALUE) (0XFF9814D4, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_309_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_309_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_397_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_397_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_397_PARITY_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_309_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_309_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_309_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_397_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_309_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
- /*Register : APERPERM_398 @ 0XFF981638</p>
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ /*Register : APERPERM_318 @ 0XFF9814F8</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_398_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_318_PERMISSION 0x2
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_398_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_318_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_398_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_318_PARITY 0x0
- Entry 398 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00E00000
- (OFFSET, MASK, VALUE) (0XFF981638, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_398_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_398_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_398_PARITY_MASK | 0 );
+ Entry 318 of the Aperture Permission List, for 32-byte IPI buffer 062 at BASE_32B + 0x000007C0
+ (OFFSET, MASK, VALUE) (0XFF9814F8, 0xF80FFFFFU ,0x08000002U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_318_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_318_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_398_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_398_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_398_PARITY_SHIFT
+ RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_318_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_318_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_318_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_398_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_318_OFFSET ,0xF80FFFFFU ,0x08000002U);
/*############################################################################################################################ */
- // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
- /*Register : APERPERM_399 @ 0XFF98163C</p>
+ // : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
+ /*Register : APERPERM_319 @ 0XFF9814FC</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_399_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_319_PERMISSION 0x20
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_399_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_319_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_399_PARITY 0x0
+ PSU_LPD_XPPU_CFG_APERPERM_319_PARITY 0x0
- Entry 399 of the Aperture Permission List, for the 1M-byte aperture at BASE_1MB + 0x00F00000
- (OFFSET, MASK, VALUE) (0XFF98163C, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_399_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_399_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_399_PARITY_MASK | 0 );
+ Entry 319 of the Aperture Permission List, for 32-byte IPI buffer 063 at BASE_32B + 0x000007E0
+ (OFFSET, MASK, VALUE) (0XFF9814FC, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_319_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_319_PARITY_MASK | 0 );
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_399_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_399_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_399_PARITY_SHIFT
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_319_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_319_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_319_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_399_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_319_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- // : APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS: DFFFFFFF
- /*Register : APERPERM_400 @ 0XFF981640</p>
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ /*Register : APERPERM_320 @ 0XFF981500</p>
This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.
- PSU_LPD_XPPU_CFG_APERPERM_400_PERMISSION 0x80000
+ PSU_LPD_XPPU_CFG_APERPERM_320_PERMISSION 0x4
1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
- PSU_LPD_XPPU_CFG_APERPERM_400_TRUSTZONE 0x1
+ PSU_LPD_XPPU_CFG_APERPERM_320_TRUSTZONE 0x1
SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
- PSU_LPD_XPPU_CFG_APERPERM_400_PARITY 0x0
-
- Entry 400 of the Aperture Permission List, for the 512M-byte aperture at BASE_512MB + 0x00000000
- (OFFSET, MASK, VALUE) (0XFF981640, 0xF80FFFFFU ,0x08080000U)
- RegMask = (LPD_XPPU_CFG_APERPERM_400_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_400_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_400_PARITY_MASK | 0 );
-
- RegVal = ((0x00080000U << LPD_XPPU_CFG_APERPERM_400_PERMISSION_SHIFT
- | 0x00000001U << LPD_XPPU_CFG_APERPERM_400_TRUSTZONE_SHIFT
- | 0x00000000U << LPD_XPPU_CFG_APERPERM_400_PARITY_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_400_OFFSET ,0xF80FFFFFU ,0x08080000U);
- /*############################################################################################################################ */
-
- // : XPPU CONTROL
- /*Register : CTRL @ 0XFF980000</p>
-
- 0=Bypass XPPU (transparent) 1=Enable XPPU permission checking
- PSU_LPD_XPPU_CFG_CTRL_ENABLE 1
-
- XPPU Control Register
- (OFFSET, MASK, VALUE) (0XFF980000, 0x00000001U ,0x00000001U)
- RegMask = (LPD_XPPU_CFG_CTRL_ENABLE_MASK | 0 );
-
- RegVal = ((0x00000001U << LPD_XPPU_CFG_CTRL_ENABLE_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (LPD_XPPU_CFG_CTRL_OFFSET ,0x00000001U ,0x00000001U);
- /*############################################################################################################################ */
-
-
- return 1;
-}
-unsigned long psu_ddr_xmpu0_data() {
- // : DDR XMPU0
-
- return 1;
-}
-unsigned long psu_ddr_xmpu1_data() {
- // : DDR XMPU1
-
- return 1;
-}
-unsigned long psu_ddr_xmpu2_data() {
- // : DDR XMPU2
-
- return 1;
-}
-unsigned long psu_ddr_xmpu3_data() {
- // : DDR XMPU3
-
- return 1;
-}
-unsigned long psu_ddr_xmpu4_data() {
- // : DDR XMPU4
-
- return 1;
-}
-unsigned long psu_ddr_xmpu5_data() {
- // : DDR XMPU5
-
- return 1;
-}
-unsigned long psu_ocm_xmpu_data() {
- // : OCM XMPU
-
- return 1;
-}
-unsigned long psu_fpd_xmpu_data() {
- // : FPD XMPU
-
- return 1;
-}
-unsigned long psu_apply_master_tz() {
- // : RPU
- // : DP TZ
- // : SATA TZ
- // : PCIE TZ
- // : USB TZ
- // : SD TZ
- // : GEM TZ
- // : QSPI TZ
- // : NAND TZ
-
- return 1;
-}
-unsigned long psu_serdes_init_data() {
- // : SERDES INITIALIZATION
- // : GT REFERENCE CLOCK SOURCE SELECTION
- /*Register : PLL_REF_SEL0 @ 0XFD410000</p>
-
- PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
- 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
- Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
- PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD
-
- PLL0 Reference Selection Register
- (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU)
- RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK | 0 );
-
- RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU);
- /*############################################################################################################################ */
-
- /*Register : PLL_REF_SEL1 @ 0XFD410004</p>
-
- PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
- 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
- Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
- PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x11
-
- PLL1 Reference Selection Register
- (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000011U)
- RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK | 0 );
-
- RegVal = ((0x00000011U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000011U);
- /*############################################################################################################################ */
-
- /*Register : PLL_REF_SEL2 @ 0XFD410008</p>
-
- PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
- 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
- Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
- PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8
+ PSU_LPD_XPPU_CFG_APERPERM_320_PARITY 0x0
- PLL2 Reference Selection Register
- (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U)
- RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK | 0 );
+ Entry 320 of the Aperture Permission List, for 32-byte IPI buffer 064 at BASE_32B + 0x00000800
+ (OFFSET, MASK, VALUE) (0XFF981500, 0xF80FFFFFU ,0x08000004U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_320_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_320_PARITY_MASK | 0 );
- RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
+ RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_320_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_320_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_320_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_320_OFFSET ,0xF80FFFFFU ,0x08000004U);
/*############################################################################################################################ */
- /*Register : PLL_REF_SEL3 @ 0XFD41000C</p>
-
- PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
- 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
- Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
- PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0x9
-
- PLL3 Reference Selection Register
- (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x00000009U)
- RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK | 0 );
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ /*Register : APERPERM_321 @ 0XFF981504</p>
- RegVal = ((0x00000009U << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x00000009U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_321_PERMISSION 0x40
- // : GT REFERENCE CLOCK FREQUENCY SELECTION
- /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_321_TRUSTZONE 0x1
- Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
- PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_321_PARITY 0x0
- Lane0 Ref Clock Selection Register
- (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U)
- RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | 0 );
+ Entry 321 of the Aperture Permission List, for 32-byte IPI buffer 065 at BASE_32B + 0x00000820
+ (OFFSET, MASK, VALUE) (0XFF981504, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_321_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_321_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_321_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_321_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_321_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_321_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864</p>
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ /*Register : APERPERM_322 @ 0XFF981508</p>
- Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
- PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_322_PERMISSION 0x8
- Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
- PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_322_TRUSTZONE 0x1
- Lane1 Ref Clock Selection Register
- (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U)
- RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK | 0 );
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_322_PARITY 0x0
- RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
- | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
+ Entry 322 of the Aperture Permission List, for 32-byte IPI buffer 066 at BASE_32B + 0x00000840
+ (OFFSET, MASK, VALUE) (0XFF981508, 0xF80FFFFFU ,0x08000008U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_322_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_322_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_322_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_322_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_322_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_322_OFFSET ,0xF80FFFFFU ,0x08000008U);
/*############################################################################################################################ */
- /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868</p>
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ /*Register : APERPERM_323 @ 0XFF98150C</p>
- Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
- PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_323_PERMISSION 0x80
- Lane2 Ref Clock Selection Register
- (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U)
- RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_323_TRUSTZONE 0x1
- RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_323_PARITY 0x0
+
+ Entry 323 of the Aperture Permission List, for 32-byte IPI buffer 067 at BASE_32B + 0x00000860
+ (OFFSET, MASK, VALUE) (0XFF98150C, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_323_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_323_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_323_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_323_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_323_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_323_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C</p>
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ /*Register : APERPERM_324 @ 0XFF981510</p>
- Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
- PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_324_PERMISSION 0x1
- Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
- PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_324_TRUSTZONE 0x1
- Lane3 Ref Clock Selection Register
- (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U)
- RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK | 0 );
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_324_PARITY 0x0
- RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
- | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
+ Entry 324 of the Aperture Permission List, for 32-byte IPI buffer 068 at BASE_32B + 0x00000880
+ (OFFSET, MASK, VALUE) (0XFF981510, 0xF80FFFFFU ,0x08000001U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_324_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_324_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_324_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_324_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_324_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_324_OFFSET ,0xF80FFFFFU ,0x08000001U);
/*############################################################################################################################ */
- // : ENABLE SPREAD SPECTRUM
- /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094</p>
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ /*Register : APERPERM_325 @ 0XFF981514</p>
- Enable/Disable coarse code satureation limiting logic
- PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_325_PERMISSION 0x10
- Test mode register 37
- (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U)
- RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_325_TRUSTZONE 0x1
- RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_325_PARITY 0x0
+
+ Entry 325 of the Aperture Permission List, for 32-byte IPI buffer 069 at BASE_32B + 0x000008A0
+ (OFFSET, MASK, VALUE) (0XFF981514, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_325_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_325_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_325_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_325_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_325_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_325_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368</p>
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ /*Register : APERPERM_334 @ 0XFF981538</p>
- Spread Spectrum No of Steps [7:0]
- PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_334_PERMISSION 0x2
- Spread Spectrum No of Steps bits 7:0
- (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U)
- RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_334_TRUSTZONE 0x1
- RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_334_PARITY 0x0
+
+ Entry 334 of the Aperture Permission List, for 32-byte IPI buffer 078 at BASE_32B + 0x000009C0
+ (OFFSET, MASK, VALUE) (0XFF981538, 0xF80FFFFFU ,0x08000002U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_334_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_334_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_334_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_334_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_334_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_334_OFFSET ,0xF80FFFFFU ,0x08000002U);
/*############################################################################################################################ */
- /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C</p>
+ // : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
+ /*Register : APERPERM_335 @ 0XFF98153C</p>
- Spread Spectrum No of Steps [10:8]
- PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_335_PERMISSION 0x20
- Spread Spectrum No of Steps bits 10:8
- (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U)
- RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_335_TRUSTZONE 0x1
- RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_335_PARITY 0x0
+
+ Entry 335 of the Aperture Permission List, for 32-byte IPI buffer 079 at BASE_32B + 0x000009E0
+ (OFFSET, MASK, VALUE) (0XFF98153C, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_335_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_335_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_335_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_335_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_335_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_335_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368</p>
-
- Spread Spectrum No of Steps bits 7:0
- (OFFSET, MASK, VALUE) (0XFD40E368, 0x00000000U ,0x00000000U)
- RegMask = ( 0 );
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ /*Register : APERPERM_336 @ 0XFF981540</p>
- RegVal = (( 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x00000000U ,0x00000000U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_336_PERMISSION 0x4
- /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_336_TRUSTZONE 0x1
- Spread Spectrum No of Steps [10:8]
- PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_336_PARITY 0x0
- Spread Spectrum No of Steps bits 10:8
- (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U)
- RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
+ Entry 336 of the Aperture Permission List, for 32-byte IPI buffer 080 at BASE_32B + 0x00000A00
+ (OFFSET, MASK, VALUE) (0XFF981540, 0xF80FFFFFU ,0x08000004U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_336_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_336_PARITY_MASK | 0 );
- RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+ RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_336_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_336_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_336_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_336_OFFSET ,0xF80FFFFFU ,0x08000004U);
/*############################################################################################################################ */
- /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368</p>
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ /*Register : APERPERM_337 @ 0XFF981544</p>
- Spread Spectrum No of Steps [7:0]
- PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_337_PERMISSION 0x40
- Spread Spectrum No of Steps bits 7:0
- (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U)
- RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_337_TRUSTZONE 0x1
- RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_337_PARITY 0x0
+
+ Entry 337 of the Aperture Permission List, for 32-byte IPI buffer 081 at BASE_32B + 0x00000A20
+ (OFFSET, MASK, VALUE) (0XFF981544, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_337_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_337_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_337_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_337_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_337_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_337_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C</p>
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ /*Register : APERPERM_338 @ 0XFF981548</p>
- Spread Spectrum No of Steps [10:8]
- PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_338_PERMISSION 0x8
+
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_338_TRUSTZONE 0x1
+
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_338_PARITY 0x0
- Spread Spectrum No of Steps bits 10:8
- (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U)
- RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
+ Entry 338 of the Aperture Permission List, for 32-byte IPI buffer 082 at BASE_32B + 0x00000A40
+ (OFFSET, MASK, VALUE) (0XFF981548, 0xF80FFFFFU ,0x08000008U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_338_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_338_PARITY_MASK | 0 );
- RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+ RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_338_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_338_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_338_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_338_OFFSET ,0xF80FFFFFU ,0x08000008U);
/*############################################################################################################################ */
- /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370</p>
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ /*Register : APERPERM_339 @ 0XFF98154C</p>
- Step Size for Spread Spectrum [7:0]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_339_PERMISSION 0x80
- Step Size for Spread Spectrum LSB
- (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU)
- RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_339_TRUSTZONE 0x1
- RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_339_PARITY 0x0
+
+ Entry 339 of the Aperture Permission List, for 32-byte IPI buffer 083 at BASE_32B + 0x00000A60
+ (OFFSET, MASK, VALUE) (0XFF98154C, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_339_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_339_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_339_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_339_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_339_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_339_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374</p>
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ /*Register : APERPERM_340 @ 0XFF981550</p>
- Step Size for Spread Spectrum [15:8]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_340_PERMISSION 0x1
- Step Size for Spread Spectrum 1
- (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U)
- RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_340_TRUSTZONE 0x1
- RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_340_PARITY 0x0
+
+ Entry 340 of the Aperture Permission List, for 32-byte IPI buffer 084 at BASE_32B + 0x00000A80
+ (OFFSET, MASK, VALUE) (0XFF981550, 0xF80FFFFFU ,0x08000001U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_340_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_340_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_340_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_340_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_340_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_340_OFFSET ,0xF80FFFFFU ,0x08000001U);
/*############################################################################################################################ */
- /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378</p>
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ /*Register : APERPERM_341 @ 0XFF981554</p>
- Step Size for Spread Spectrum [23:16]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_341_PERMISSION 0x10
- Step Size for Spread Spectrum 2
- (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U)
- RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_341_TRUSTZONE 0x1
- RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_341_PARITY 0x0
+
+ Entry 341 of the Aperture Permission List, for 32-byte IPI buffer 085 at BASE_32B + 0x00000AA0
+ (OFFSET, MASK, VALUE) (0XFF981554, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_341_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_341_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C</p>
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ /*Register : APERPERM_350 @ 0XFF981578</p>
- Step Size for Spread Spectrum [25:24]
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_350_PERMISSION 0x2
- Enable/Disable test mode force on SS step size
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_350_TRUSTZONE 0x1
- Enable/Disable test mode force on SS no of steps
- PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_350_PARITY 0x0
- Enable force on enable Spread Spectrum
- (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U)
- RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 );
+ Entry 350 of the Aperture Permission List, for 32-byte IPI buffer 094 at BASE_32B + 0x00000BC0
+ (OFFSET, MASK, VALUE) (0XFF981578, 0xF80FFFFFU ,0x08000002U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_350_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_350_PARITY_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
- | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
- | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+ RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_350_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_350_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_350_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_350_OFFSET ,0xF80FFFFFU ,0x08000002U);
/*############################################################################################################################ */
- /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370</p>
+ // : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
+ /*Register : APERPERM_351 @ 0XFF98157C</p>
- Step Size for Spread Spectrum [7:0]
- PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_351_PERMISSION 0x20
- Step Size for Spread Spectrum LSB
- (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U)
- RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_351_TRUSTZONE 0x1
- RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_351_PARITY 0x0
+
+ Entry 351 of the Aperture Permission List, for 32-byte IPI buffer 095 at BASE_32B + 0x00000BE0
+ (OFFSET, MASK, VALUE) (0XFF98157C, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_351_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_351_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_351_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_351_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_351_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_351_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374</p>
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ /*Register : APERPERM_352 @ 0XFF981580</p>
- Step Size for Spread Spectrum [15:8]
- PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_352_PERMISSION 0x4
- Step Size for Spread Spectrum 1
- (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U)
- RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_352_TRUSTZONE 0x1
- RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_352_PARITY 0x0
+
+ Entry 352 of the Aperture Permission List, for 32-byte IPI buffer 096 at BASE_32B + 0x00000C00
+ (OFFSET, MASK, VALUE) (0XFF981580, 0xF80FFFFFU ,0x08000004U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_352_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_352_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000004U << LPD_XPPU_CFG_APERPERM_352_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_352_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_352_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_352_OFFSET ,0xF80FFFFFU ,0x08000004U);
/*############################################################################################################################ */
- /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378</p>
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ /*Register : APERPERM_353 @ 0XFF981584</p>
- Step Size for Spread Spectrum [23:16]
- PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_353_PERMISSION 0x40
- Step Size for Spread Spectrum 2
- (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U)
- RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_353_TRUSTZONE 0x1
- RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_353_PARITY 0x0
+
+ Entry 353 of the Aperture Permission List, for 32-byte IPI buffer 097 at BASE_32B + 0x00000C20
+ (OFFSET, MASK, VALUE) (0XFF981584, 0xF80FFFFFU ,0x08000040U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_353_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_353_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000040U << LPD_XPPU_CFG_APERPERM_353_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_353_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_353_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_353_OFFSET ,0xF80FFFFFU ,0x08000040U);
/*############################################################################################################################ */
- /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C</p>
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ /*Register : APERPERM_354 @ 0XFF981588</p>
- Step Size for Spread Spectrum [25:24]
- PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_354_PERMISSION 0x8
- Enable/Disable test mode force on SS step size
- PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_354_TRUSTZONE 0x1
- Enable/Disable test mode force on SS no of steps
- PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_354_PARITY 0x0
- Enable force on enable Spread Spectrum
- (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U)
- RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 );
+ Entry 354 of the Aperture Permission List, for 32-byte IPI buffer 098 at BASE_32B + 0x00000C40
+ (OFFSET, MASK, VALUE) (0XFF981588, 0xF80FFFFFU ,0x08000008U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_354_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_354_PARITY_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
- | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
- | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+ RegVal = ((0x00000008U << LPD_XPPU_CFG_APERPERM_354_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_354_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_354_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_354_OFFSET ,0xF80FFFFFU ,0x08000008U);
/*############################################################################################################################ */
- /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370</p>
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ /*Register : APERPERM_355 @ 0XFF98158C</p>
+
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_355_PERMISSION 0x80
+
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_355_TRUSTZONE 0x1
- Step Size for Spread Spectrum [7:0]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xD3
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_355_PARITY 0x0
- Step Size for Spread Spectrum LSB
- (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000D3U)
- RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
+ Entry 355 of the Aperture Permission List, for 32-byte IPI buffer 099 at BASE_32B + 0x00000C60
+ (OFFSET, MASK, VALUE) (0XFF98158C, 0xF80FFFFFU ,0x08000080U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_355_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_355_PARITY_MASK | 0 );
- RegVal = ((0x000000D3U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+ RegVal = ((0x00000080U << LPD_XPPU_CFG_APERPERM_355_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_355_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_355_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000D3U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_355_OFFSET ,0xF80FFFFFU ,0x08000080U);
/*############################################################################################################################ */
- /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374</p>
-
- Step Size for Spread Spectrum [15:8]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xDA
-
- Step Size for Spread Spectrum 1
- (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000DAU)
- RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ /*Register : APERPERM_356 @ 0XFF981590</p>
- RegVal = ((0x000000DAU << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000DAU);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_356_PERMISSION 0x1
- /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_356_TRUSTZONE 0x1
- Step Size for Spread Spectrum [23:16]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_356_PARITY 0x0
- Step Size for Spread Spectrum 2
- (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000002U)
- RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
+ Entry 356 of the Aperture Permission List, for 32-byte IPI buffer 100 at BASE_32B + 0x00000C80
+ (OFFSET, MASK, VALUE) (0XFF981590, 0xF80FFFFFU ,0x08000001U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_356_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_356_PARITY_MASK | 0 );
- RegVal = ((0x00000002U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_APERPERM_356_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_356_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_356_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_356_OFFSET ,0xF80FFFFFU ,0x08000001U);
/*############################################################################################################################ */
- /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C</p>
-
- Step Size for Spread Spectrum [25:24]
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ /*Register : APERPERM_357 @ 0XFF981594</p>
- Enable/Disable test mode force on SS step size
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_357_PERMISSION 0x10
- Enable/Disable test mode force on SS no of steps
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_357_TRUSTZONE 0x1
- Enable test mode forcing on enable Spread Spectrum
- PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_357_PARITY 0x0
- Enable force on enable Spread Spectrum
- (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U)
- RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK | 0 );
+ Entry 357 of the Aperture Permission List, for 32-byte IPI buffer 101 at BASE_32B + 0x00000CA0
+ (OFFSET, MASK, VALUE) (0XFF981594, 0xF80FFFFFU ,0x08000010U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_357_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_357_PARITY_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
- | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
- | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
- | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
+ RegVal = ((0x00000010U << LPD_XPPU_CFG_APERPERM_357_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_357_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_357_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_357_OFFSET ,0xF80FFFFFU ,0x08000010U);
/*############################################################################################################################ */
- /*Register : L2_TM_DIG_6 @ 0XFD40906C</p>
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ /*Register : APERPERM_366 @ 0XFF9815B8</p>
- Bypass Descrambler
- PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_366_PERMISSION 0x2
- Enable Bypass for <1> TM_DIG_CTRL_6
- PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_366_TRUSTZONE 0x1
- Data path test modes in decoder and descram
- (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U)
- RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 );
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_366_PARITY 0x0
- RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
- | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
+ Entry 366 of the Aperture Permission List, for 32-byte IPI buffer 110 at BASE_32B + 0x00000DC0
+ (OFFSET, MASK, VALUE) (0XFF9815B8, 0xF80FFFFFU ,0x08000002U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_366_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_366_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_366_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_366_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_366_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_366_OFFSET ,0xF80FFFFFU ,0x08000002U);
/*############################################################################################################################ */
- /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4</p>
+ // : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
+ /*Register : APERPERM_367 @ 0XFF9815BC</p>
- Bypass scrambler signal
- PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_367_PERMISSION 0x20
- Enable/disable scrambler bypass signal
- PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_367_TRUSTZONE 0x1
- MPHY PLL Gear and bypass scrambler
- (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U)
- RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 );
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_367_PARITY 0x0
- RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
- | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
+ Entry 367 of the Aperture Permission List, for 32-byte IPI buffer 111 at BASE_32B + 0x00000DE0
+ (OFFSET, MASK, VALUE) (0XFF9815BC, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_367_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_367_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_367_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_367_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_367_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_367_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_368 @ 0XFF9815C0</p>
- Enable test mode force on fractional mode enable
- PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_368_PERMISSION 0x24
- Fractional feedback division control and fractional value for feedback division bits 26:24
- (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U)
- RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_368_TRUSTZONE 0x1
- RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_368_PARITY 0x0
+
+ Entry 368 of the Aperture Permission List, for 32-byte IPI buffer 112 at BASE_32B + 0x00000E00
+ (OFFSET, MASK, VALUE) (0XFF9815C0, 0xF80FFFFFU ,0x08000024U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_368_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_368_PARITY_MASK | 0 );
+
+ RegVal = ((0x00000024U << LPD_XPPU_CFG_APERPERM_368_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_368_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_368_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_368_OFFSET ,0xF80FFFFFU ,0x08000024U);
/*############################################################################################################################ */
- /*Register : L3_TM_DIG_6 @ 0XFD40D06C</p>
-
- Bypass 8b10b decoder
- PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_369 @ 0XFF9815C4</p>
- Enable Bypass for <3> TM_DIG_CTRL_6
- PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_369_PERMISSION 0x42
- Bypass Descrambler
- PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_369_TRUSTZONE 0x1
- Enable Bypass for <1> TM_DIG_CTRL_6
- PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_369_PARITY 0x0
- Data path test modes in decoder and descram
- (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU)
- RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 );
+ Entry 369 of the Aperture Permission List, for 32-byte IPI buffer 113 at BASE_32B + 0x00000E20
+ (OFFSET, MASK, VALUE) (0XFF9815C4, 0xF80FFFFFU ,0x08000042U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_369_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_369_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
- | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
- | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
- | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
+ RegVal = ((0x00000042U << LPD_XPPU_CFG_APERPERM_369_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_369_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_369_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_369_OFFSET ,0xF80FFFFFU ,0x08000042U);
/*############################################################################################################################ */
- /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_370 @ 0XFF9815C8</p>
- Enable/disable encoder bypass signal
- PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_370_PERMISSION 0x28
- Bypass scrambler signal
- PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_370_TRUSTZONE 0x1
- Enable/disable scrambler bypass signal
- PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_370_PARITY 0x0
- MPHY PLL Gear and bypass scrambler
- (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU)
- RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 );
+ Entry 370 of the Aperture Permission List, for 32-byte IPI buffer 114 at BASE_32B + 0x00000E40
+ (OFFSET, MASK, VALUE) (0XFF9815C8, 0xF80FFFFFU ,0x08000028U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_370_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_370_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
- | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
- | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
+ RegVal = ((0x00000028U << LPD_XPPU_CFG_APERPERM_370_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_370_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_370_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_370_OFFSET ,0xF80FFFFFU ,0x08000028U);
/*############################################################################################################################ */
- /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00</p>
-
- PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
- PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21
-
- Opmode Info
- (OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U)
- RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK | 0 );
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_371 @ 0XFF9815CC</p>
- RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_371_PERMISSION 0x82
- // : ENABLE CHICKEN BIT FOR PCIE AND USB
- /*Register : L0_TM_AUX_0 @ 0XFD4010CC</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_371_TRUSTZONE 0x1
- Spare- not used
- PSU_SERDES_L0_TM_AUX_0_BIT_2 1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_371_PARITY 0x0
- Spare registers
- (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U)
- RegMask = (SERDES_L0_TM_AUX_0_BIT_2_MASK | 0 );
+ Entry 371 of the Aperture Permission List, for 32-byte IPI buffer 115 at BASE_32B + 0x00000E60
+ (OFFSET, MASK, VALUE) (0XFF9815CC, 0xF80FFFFFU ,0x08000082U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_371_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_371_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L0_TM_AUX_0_BIT_2_SHIFT
+ RegVal = ((0x00000082U << LPD_XPPU_CFG_APERPERM_371_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_371_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_371_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_371_OFFSET ,0xF80FFFFFU ,0x08000082U);
/*############################################################################################################################ */
- /*Register : L2_TM_AUX_0 @ 0XFD4090CC</p>
-
- Spare- not used
- PSU_SERDES_L2_TM_AUX_0_BIT_2 1
-
- Spare registers
- (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U)
- RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK | 0 );
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_372 @ 0XFF9815D0</p>
- RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_372_PERMISSION 0x21
- // : ENABLING EYE SURF
- /*Register : L0_TM_DIG_8 @ 0XFD401074</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_372_TRUSTZONE 0x1
- Enable Eye Surf
- PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_372_PARITY 0x0
- Test modes for Elastic buffer and enabling Eye Surf
- (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U)
- RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+ Entry 372 of the Aperture Permission List, for 32-byte IPI buffer 116 at BASE_32B + 0x00000E80
+ (OFFSET, MASK, VALUE) (0XFF9815D0, 0xF80FFFFFU ,0x08000021U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_372_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_372_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ RegVal = ((0x00000021U << LPD_XPPU_CFG_APERPERM_372_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_372_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_372_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_372_OFFSET ,0xF80FFFFFU ,0x08000021U);
/*############################################################################################################################ */
- /*Register : L1_TM_DIG_8 @ 0XFD405074</p>
-
- Enable Eye Surf
- PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1
-
- Test modes for Elastic buffer and enabling Eye Surf
- (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U)
- RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_373 @ 0XFF9815D4</p>
- RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_373_PERMISSION 0x12
- /*Register : L2_TM_DIG_8 @ 0XFD409074</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_373_TRUSTZONE 0x1
- Enable Eye Surf
- PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_373_PARITY 0x0
- Test modes for Elastic buffer and enabling Eye Surf
- (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U)
- RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+ Entry 373 of the Aperture Permission List, for 32-byte IPI buffer 117 at BASE_32B + 0x00000EA0
+ (OFFSET, MASK, VALUE) (0XFF9815D4, 0xF80FFFFFU ,0x08000012U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_373_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_373_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
+ RegVal = ((0x00000012U << LPD_XPPU_CFG_APERPERM_373_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_373_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_373_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_373_OFFSET ,0xF80FFFFFU ,0x08000012U);
/*############################################################################################################################ */
- /*Register : L3_TM_DIG_8 @ 0XFD40D074</p>
-
- Enable Eye Surf
- PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1
-
- Test modes for Elastic buffer and enabling Eye Surf
- (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U)
- RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_374 @ 0XFF9815D8</p>
- RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_374_PERMISSION 0x20
- // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS
- /*Register : L0_TM_MISC2 @ 0XFD40189C</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_374_TRUSTZONE 0x1
- ILL calib counts BYPASSED with calcode bits
- PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_374_PARITY 0x0
- sampler cal
- (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U)
- RegMask = (SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+ Entry 374 of the Aperture Permission List, for 32-byte IPI buffer 118 at BASE_32B + 0x00000EC0
+ (OFFSET, MASK, VALUE) (0XFF9815D8, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_374_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_374_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_374_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_374_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_374_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_374_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L0_TM_IQ_ILL1 @ 0XFD4018F8</p>
-
- IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
- PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64
-
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U)
- RegMask = (SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_375 @ 0XFF9815DC</p>
- RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000064U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_375_PERMISSION 0x2
- /*Register : L0_TM_IQ_ILL2 @ 0XFD4018FC</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_375_TRUSTZONE 0x1
- IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
- PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_375_PARITY 0x0
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U)
- RegMask = (SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+ Entry 375 of the Aperture Permission List, for 32-byte IPI buffer 119 at BASE_32B + 0x00000EE0
+ (OFFSET, MASK, VALUE) (0XFF9815DC, 0xF80FFFFFU ,0x08000002U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_375_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_375_PARITY_MASK | 0 );
- RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+ RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_375_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_375_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_375_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000064U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_375_OFFSET ,0xF80FFFFFU ,0x08000002U);
/*############################################################################################################################ */
- /*Register : L0_TM_ILL12 @ 0XFD401990</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_376 @ 0XFF9815E0</p>
- G1A pll ctr bypass value
- PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_376_PERMISSION 0x20
- ill pll counter values
- (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U)
- RegMask = (SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_376_TRUSTZONE 0x1
+
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_376_PARITY 0x0
+
+ Entry 376 of the Aperture Permission List, for 32-byte IPI buffer 120 at BASE_32B + 0x00000F00
+ (OFFSET, MASK, VALUE) (0XFF9815E0, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_376_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_376_PARITY_MASK | 0 );
- RegVal = ((0x00000011U << SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_376_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_376_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_376_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_ILL12_OFFSET ,0x000000FFU ,0x00000011U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_376_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L0_TM_E_ILL1 @ 0XFD401924</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_377 @ 0XFF9815E4</p>
- E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
- PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_377_PERMISSION 0x2
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U)
- RegMask = (SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_377_TRUSTZONE 0x1
+
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_377_PARITY 0x0
+
+ Entry 377 of the Aperture Permission List, for 32-byte IPI buffer 121 at BASE_32B + 0x00000F20
+ (OFFSET, MASK, VALUE) (0XFF9815E4, 0xF80FFFFFU ,0x08000002U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_377_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_377_PARITY_MASK | 0 );
- RegVal = ((0x00000004U << SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_377_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_377_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_377_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_E_ILL1_OFFSET ,0x000000FFU ,0x00000004U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_377_OFFSET ,0xF80FFFFFU ,0x08000002U);
/*############################################################################################################################ */
- /*Register : L0_TM_E_ILL2 @ 0XFD401928</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_378 @ 0XFF9815E8</p>
- E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
- PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_378_PERMISSION 0x20
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU)
- RegMask = (SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_378_TRUSTZONE 0x1
+
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_378_PARITY 0x0
+
+ Entry 378 of the Aperture Permission List, for 32-byte IPI buffer 122 at BASE_32B + 0x00000F40
+ (OFFSET, MASK, VALUE) (0XFF9815E8, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_378_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_378_PARITY_MASK | 0 );
- RegVal = ((0x000000FEU << SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_378_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_378_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_378_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_E_ILL2_OFFSET ,0x000000FFU ,0x000000FEU);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_378_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L0_TM_IQ_ILL3 @ 0XFD401900</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_379 @ 0XFF9815EC</p>
+
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_379_PERMISSION 0x2
- IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
- PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_379_TRUSTZONE 0x1
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U)
- RegMask = (SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_379_PARITY 0x0
+
+ Entry 379 of the Aperture Permission List, for 32-byte IPI buffer 123 at BASE_32B + 0x00000F60
+ (OFFSET, MASK, VALUE) (0XFF9815EC, 0xF80FFFFFU ,0x08000002U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_379_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_379_PARITY_MASK | 0 );
- RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+ RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_379_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_379_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_379_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_379_OFFSET ,0xF80FFFFFU ,0x08000002U);
/*############################################################################################################################ */
- /*Register : L0_TM_E_ILL3 @ 0XFD40192C</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_380 @ 0XFF9815F0</p>
- E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
- PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_380_PERMISSION 0x20
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U)
- RegMask = (SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_380_TRUSTZONE 0x1
+
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_380_PARITY 0x0
+
+ Entry 380 of the Aperture Permission List, for 32-byte IPI buffer 124 at BASE_32B + 0x00000F80
+ (OFFSET, MASK, VALUE) (0XFF9815F0, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_380_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_380_PARITY_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_380_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_380_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_380_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_380_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L0_TM_ILL8 @ 0XFD401980</p>
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_381 @ 0XFF9815F4</p>
+
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_381_PERMISSION 0x2
+
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_381_TRUSTZONE 0x1
- ILL calibration code change wait time
- PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_381_PARITY 0x0
- ILL cal routine control
- (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU)
- RegMask = (SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+ Entry 381 of the Aperture Permission List, for 32-byte IPI buffer 125 at BASE_32B + 0x00000FA0
+ (OFFSET, MASK, VALUE) (0XFF9815F4, 0xF80FFFFFU ,0x08000002U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_381_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_381_PARITY_MASK | 0 );
- RegVal = ((0x000000FFU << SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ RegVal = ((0x00000002U << LPD_XPPU_CFG_APERPERM_381_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_381_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_381_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_381_OFFSET ,0xF80FFFFFU ,0x08000002U);
/*############################################################################################################################ */
- /*Register : L0_TM_IQ_ILL8 @ 0XFD401914</p>
-
- IQ ILL polytrim bypass value
- PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
-
- iqpi polytrim
- (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U)
- RegMask = (SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_382 @ 0XFF9815F8</p>
- RegVal = ((0x000000F7U << SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_382_PERMISSION 0x20
- /*Register : L0_TM_IQ_ILL9 @ 0XFD401918</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_382_TRUSTZONE 0x1
- bypass IQ polytrim
- PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_382_PARITY 0x0
- enables for lf,constant gm trim and polytirm
- (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+ Entry 382 of the Aperture Permission List, for 32-byte IPI buffer 126 at BASE_32B + 0x00000FC0
+ (OFFSET, MASK, VALUE) (0XFF9815F8, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_382_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_382_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L0_TM_E_ILL8 @ 0XFD401940</p>
-
- E ILL polytrim bypass value
- PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
-
- epi polytrim
- (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U)
- RegMask = (SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+ // : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
+ /*Register : APERPERM_383 @ 0XFF9815FC</p>
- RegVal = ((0x000000F7U << SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_383_PERMISSION 0x20
- /*Register : L0_TM_E_ILL9 @ 0XFD401944</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_383_TRUSTZONE 0x1
- bypass E polytrim
- PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_383_PARITY 0x0
- enables for lf,constant gm trim and polytirm
- (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+ Entry 383 of the Aperture Permission List, for 32-byte IPI buffer 127 at BASE_32B + 0x00000FE0
+ (OFFSET, MASK, VALUE) (0XFF9815FC, 0xF80FFFFFU ,0x08000020U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_383_PARITY_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ RegVal = ((0x00000020U << LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_383_OFFSET ,0xF80FFFFFU ,0x08000020U);
/*############################################################################################################################ */
- /*Register : L2_TM_MISC2 @ 0XFD40989C</p>
+ // : APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF
+ // : APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF
+ // : APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFFFF
+ // : APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFFFF
+ // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
+ // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
+ // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
+ // : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
+ // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
+ // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
+ // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
+ // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
+ // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
+ // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
+ // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
+ // : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
+ // : APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS: DFFFFFFF
+ // : XPPU CONTROL
+ /*Register : err_ctrl @ 0XFF9CFFEC</p>
- ILL calib counts BYPASSED with calcode bits
- PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+ Whether an APB access to the "hole" region and to an unimplemented register space causes PSLVERR
+ PSU_LPD_XPPU_SINK_ERR_CTRL_PSLVERR 1
- sampler cal
- (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U)
- RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+ Error control register
+ (OFFSET, MASK, VALUE) (0XFF9CFFEC, 0x00000001U ,0x00000001U)
+ RegMask = (LPD_XPPU_SINK_ERR_CTRL_PSLVERR_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_SINK_ERR_CTRL_PSLVERR_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ PSU_Mask_Write (LPD_XPPU_SINK_ERR_CTRL_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8</p>
+ /*Register : CTRL @ 0XFF980000</p>
- IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
- PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A
+ 0=Bypass XPPU (transparent) 1=Enable XPPU permission checking
+ PSU_LPD_XPPU_CFG_CTRL_ENABLE 1
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU)
- RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+ XPPU Control Register
+ (OFFSET, MASK, VALUE) (0XFF980000, 0x00000001U ,0x00000001U)
+ RegMask = (LPD_XPPU_CFG_CTRL_ENABLE_MASK | 0 );
- RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_CTRL_ENABLE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU);
+ PSU_Mask_Write (LPD_XPPU_CFG_CTRL_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC</p>
-
- IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
- PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A
-
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU)
- RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+ // : XPPU INTERRUPT ENABLE
+ /*Register : IEN @ 0XFF980018</p>
- RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU);
- /*############################################################################################################################ */
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1
- /*Register : L2_TM_ILL12 @ 0XFD409990</p>
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1
- G1A pll ctr bypass value
- PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1
- ill pll counter values
- (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U)
- RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1
- RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U);
- /*############################################################################################################################ */
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1
- /*Register : L2_TM_E_ILL1 @ 0XFD409924</p>
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1
- E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
- PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE
+ See Interuppt Status Register for details
+ PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU)
- RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+ Interrupt Enable Register
+ (OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU)
+ RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK | 0 );
- RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU);
+ PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU);
/*############################################################################################################################ */
- /*Register : L2_TM_E_ILL2 @ 0XFD409928</p>
-
- E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
- PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U)
- RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+ return 1;
+}
+unsigned long psu_ddr_xmpu0_data() {
+ // : DDR XMPU0
- RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U);
- /*############################################################################################################################ */
+ return 1;
+}
+unsigned long psu_ddr_xmpu1_data() {
+ // : DDR XMPU1
- /*Register : L2_TM_IQ_ILL3 @ 0XFD409900</p>
+ return 1;
+}
+unsigned long psu_ddr_xmpu2_data() {
+ // : DDR XMPU2
- IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
- PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A
+ return 1;
+}
+unsigned long psu_ddr_xmpu3_data() {
+ // : DDR XMPU3
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU)
- RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+ return 1;
+}
+unsigned long psu_ddr_xmpu4_data() {
+ // : DDR XMPU4
- RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU);
- /*############################################################################################################################ */
+ return 1;
+}
+unsigned long psu_ddr_xmpu5_data() {
+ // : DDR XMPU5
- /*Register : L2_TM_E_ILL3 @ 0XFD40992C</p>
+ return 1;
+}
+unsigned long psu_ocm_xmpu_data() {
+ // : OCM XMPU
- E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
- PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
+ return 1;
+}
+unsigned long psu_fpd_xmpu_data() {
+ // : FPD XMPU
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U)
- RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+ return 1;
+}
+unsigned long psu_protection_lock_data() {
+ // : LOCKING PROTECTION MODULE
+ // : XPPU LOCK
+ // : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
+ /*Register : APERPERM_152 @ 0XFF981260</p>
- RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
- /*############################################################################################################################ */
+ This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.
+ PSU_LPD_XPPU_CFG_APERPERM_152_PERMISSION 0x0
- /*Register : L2_TM_ILL8 @ 0XFD409980</p>
+ 1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed
+ PSU_LPD_XPPU_CFG_APERPERM_152_TRUSTZONE 0x1
- ILL calibration code change wait time
- PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+ SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0
+ PSU_LPD_XPPU_CFG_APERPERM_152_PARITY 0x0
- ILL cal routine control
- (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU)
- RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+ Entry 152 of the Aperture Permission List, for the 64K-byte aperture at BASE_64KB + 0x00980000
+ (OFFSET, MASK, VALUE) (0XFF981260, 0xF80FFFFFU ,0x08000000U)
+ RegMask = (LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK | LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK | LPD_XPPU_CFG_APERPERM_152_PARITY_MASK | 0 );
- RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ RegVal = ((0x00000000U << LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT
+ | 0x00000001U << LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT
+ | 0x00000000U << LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ PSU_Mask_Write (LPD_XPPU_CFG_APERPERM_152_OFFSET ,0xF80FFFFFU ,0x08000000U);
/*############################################################################################################################ */
- /*Register : L2_TM_IQ_ILL8 @ 0XFD409914</p>
+ // : XMPU LOCK
- IQ ILL polytrim bypass value
- PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+ return 1;
+}
+unsigned long psu_apply_master_tz() {
+ // : RPU
+ // : DP TZ
+ // : SATA TZ
+ // : PCIE TZ
+ // : USB TZ
+ // : SD TZ
+ // : GEM TZ
+ // : QSPI TZ
+ // : NAND TZ
- iqpi polytrim
- (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U)
- RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+ return 1;
+}
+unsigned long psu_serdes_init_data() {
+ // : SERDES INITIALIZATION
+ // : GT REFERENCE CLOCK SOURCE SELECTION
+ /*Register : PLL_REF_SEL0 @ 0XFD410000</p>
+
+ PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
+ 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+ Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+ PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0x9
+
+ PLL0 Reference Selection Register
+ (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x00000009U)
+ RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK | 0 );
- RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+ RegVal = ((0x00000009U << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x00000009U);
/*############################################################################################################################ */
- /*Register : L2_TM_IQ_ILL9 @ 0XFD409918</p>
+ /*Register : PLL_REF_SEL1 @ 0XFD410004</p>
- bypass IQ polytrim
- PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+ PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
+ 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+ Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+ PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9
- enables for lf,constant gm trim and polytirm
- (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+ PLL1 Reference Selection Register
+ (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U)
+ RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U);
/*############################################################################################################################ */
- /*Register : L2_TM_E_ILL8 @ 0XFD409940</p>
+ /*Register : PLL_REF_SEL2 @ 0XFD410008</p>
- E ILL polytrim bypass value
- PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+ PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
+ 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+ Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+ PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8
- epi polytrim
- (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U)
- RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+ PLL2 Reference Selection Register
+ (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U)
+ RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK | 0 );
- RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U);
/*############################################################################################################################ */
- /*Register : L2_TM_E_ILL9 @ 0XFD409944</p>
+ /*Register : PLL_REF_SEL3 @ 0XFD41000C</p>
- bypass E polytrim
- PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+ PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
+ 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+ Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+ PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF
- enables for lf,constant gm trim and polytirm
- (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+ PLL3 Reference Selection Register
+ (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU)
+ RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU);
/*############################################################################################################################ */
- /*Register : L3_TM_MISC2 @ 0XFD40D89C</p>
+ // : GT REFERENCE CLOCK FREQUENCY SELECTION
+ /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860</p>
- ILL calib counts BYPASSED with calcode bits
- PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
+ Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
+ PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x0
- sampler cal
- (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U)
- RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
+ Bit 3 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
+ PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3 0x1
- RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+ Lane0 Ref Clock Selection Register
+ (OFFSET, MASK, VALUE) (0XFD402860, 0x00000088U ,0x00000008U)
+ RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
+ | 0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
+ PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
/*############################################################################################################################ */
- /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8</p>
+ /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864</p>
- IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
- PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x96
+ Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
+ PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x00000096U)
- RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
+ Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
+ PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1
+
+ Lane1 Ref Clock Selection Register
+ (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U)
+ RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK | 0 );
- RegVal = ((0x00000096U << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+ RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
+ | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000096U);
+ PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
/*############################################################################################################################ */
- /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC</p>
+ /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868</p>
- IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
- PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x96
+ Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
+ PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x00000096U)
- RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
+ Lane2 Ref Clock Selection Register
+ (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK | 0 );
- RegVal = ((0x00000096U << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+ RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000096U);
+ PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
/*############################################################################################################################ */
- /*Register : L3_TM_ILL12 @ 0XFD40D990</p>
+ /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C</p>
- G1A pll ctr bypass value
- PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1
+ Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
+ PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0
- ill pll counter values
- (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U)
- RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
+ Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
+ PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1
- RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+ Lane3 Ref Clock Selection Register
+ (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U)
+ RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
+ | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U);
+ PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U);
/*############################################################################################################################ */
- /*Register : L3_TM_E_ILL1 @ 0XFD40D924</p>
+ // : ENABLE SPREAD SPECTRUM
+ /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094</p>
- E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
- PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C
+ Enable/Disable coarse code satureation limiting logic
+ PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU)
- RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
+ Test mode register 37
+ (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK | 0 );
- RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU);
+ PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U);
/*############################################################################################################################ */
- /*Register : L3_TM_E_ILL2 @ 0XFD40D928</p>
+ /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368</p>
- E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
- PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39
+ Spread Spectrum No of Steps [7:0]
+ PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U)
- RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
+ Spread Spectrum No of Steps bits 7:0
+ (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U)
+ RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
- RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U);
+ PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U);
/*############################################################################################################################ */
- /*Register : L3_TM_ILL11 @ 0XFD40D98C</p>
+ /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C</p>
- G2A_PCIe1 PLL ctr bypass value
- PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2
+ Spread Spectrum No of Steps [10:8]
+ PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03
- ill pll counter values
- (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U)
- RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK | 0 );
+ Spread Spectrum No of Steps bits 10:8
+ (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U)
+ RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
- RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
+ RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U);
+ PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
/*############################################################################################################################ */
- /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900</p>
+ /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368</p>
- IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
- PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x96
+ Spread Spectrum No of Steps [7:0]
+ PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0
- iqpi cal code
- (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x00000096U)
- RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+ Spread Spectrum No of Steps bits 7:0
+ (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U)
+ RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
- RegVal = ((0x00000096U << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+ RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000096U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U);
/*############################################################################################################################ */
- /*Register : L3_TM_E_ILL3 @ 0XFD40D92C</p>
+ /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C</p>
- E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
- PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64
+ Spread Spectrum No of Steps [10:8]
+ PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
- epi cal code
- (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U)
- RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
+ Spread Spectrum No of Steps bits 10:8
+ (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U)
+ RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
- RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
/*############################################################################################################################ */
- /*Register : L3_TM_ILL8 @ 0XFD40D980</p>
+ /*Register : L0_PLL_SS_STEPS_0_LSB @ 0XFD402368</p>
- ILL calibration code change wait time
- PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
+ Spread Spectrum No of Steps [7:0]
+ PSU_SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
- ILL cal routine control
- (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU)
- RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
+ Spread Spectrum No of Steps bits 7:0
+ (OFFSET, MASK, VALUE) (0XFD402368, 0x000000FFU ,0x00000058U)
+ RegMask = (SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
- RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ RegVal = ((0x00000058U << SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ PSU_Mask_Write (SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U);
/*############################################################################################################################ */
- /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914</p>
+ /*Register : L0_PLL_SS_STEPS_1_MSB @ 0XFD40236C</p>
- IQ ILL polytrim bypass value
- PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
+ Spread Spectrum No of Steps [10:8]
+ PSU_SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
- iqpi polytrim
- (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U)
- RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
+ Spread Spectrum No of Steps bits 10:8
+ (OFFSET, MASK, VALUE) (0XFD40236C, 0x00000007U ,0x00000003U)
+ RegMask = (SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
- RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+ RegVal = ((0x00000003U << SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ PSU_Mask_Write (SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
/*############################################################################################################################ */
- /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918</p>
+ /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368</p>
- bypass IQ polytrim
- PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
+ Spread Spectrum No of Steps [7:0]
+ PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
- enables for lf,constant gm trim and polytirm
- (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
+ Spread Spectrum No of Steps bits 7:0
+ (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U)
+ RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+ RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U);
/*############################################################################################################################ */
- /*Register : L3_TM_E_ILL8 @ 0XFD40D940</p>
+ /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C</p>
- E ILL polytrim bypass value
- PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+ Spread Spectrum No of Steps [10:8]
+ PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
- epi polytrim
- (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U)
- RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+ Spread Spectrum No of Steps bits 10:8
+ (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U)
+ RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 );
- RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
/*############################################################################################################################ */
- /*Register : L3_TM_E_ILL9 @ 0XFD40D944</p>
+ /*Register : L0_PLL_SS_STEP_SIZE_0_LSB @ 0XFD402370</p>
- bypass E polytrim
- PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+ Step Size for Spread Spectrum [7:0]
+ PSU_SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
- enables for lf,constant gm trim and polytirm
- (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+ Step Size for Spread Spectrum LSB
+ (OFFSET, MASK, VALUE) (0XFD402370, 0x000000FFU ,0x0000007CU)
+ RegMask = (SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ RegVal = ((0x0000007CU << SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU);
/*############################################################################################################################ */
- // : PCIE PLL SETTINGS
- // : GT LANE SETTINGS
- /*Register : ICM_CFG0 @ 0XFD410010</p>
-
- Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
- , 7 - Unused
- PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1
+ /*Register : L0_PLL_SS_STEP_SIZE_1 @ 0XFD402374</p>
- Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
- 7 - Unused
- PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4
+ Step Size for Spread Spectrum [15:8]
+ PSU_SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
- ICM Configuration Register 0
- (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U)
- RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK | 0 );
+ Step Size for Spread Spectrum 1
+ (OFFSET, MASK, VALUE) (0XFD402374, 0x000000FFU ,0x00000033U)
+ RegMask = (SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
- | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
+ RegVal = ((0x00000033U << SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U);
+ PSU_Mask_Write (SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U);
/*############################################################################################################################ */
- /*Register : ICM_CFG1 @ 0XFD410014</p>
-
- Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
- 7 - Unused
- PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3
+ /*Register : L0_PLL_SS_STEP_SIZE_2 @ 0XFD402378</p>
- Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
- 7 - Unused
- PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2
+ Step Size for Spread Spectrum [23:16]
+ PSU_SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
- ICM Configuration Register 1
- (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U)
- RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK | 0 );
+ Step Size for Spread Spectrum 2
+ (OFFSET, MASK, VALUE) (0XFD402378, 0x000000FFU ,0x00000002U)
+ RegMask = (SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
- RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
- | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
+ RegVal = ((0x00000002U << SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U);
+ PSU_Mask_Write (SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
/*############################################################################################################################ */
- // : CHECKING PLL LOCK
- // : ENABLE SERIAL DATA MUX DEEMPH
- /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4</p>
-
- Enable/disable DP post2 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
-
- Override enable/disable of DP post2 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
+ /*Register : L0_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40237C</p>
- Override enable/disable of DP post1 path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
+ Step Size for Spread Spectrum [25:24]
+ PSU_SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
- Enable/disable DP main path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
+ Enable/Disable test mode force on SS step size
+ PSU_SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
- Override enable/disable of DP main path
- PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
+ Enable/Disable test mode force on SS no of steps
+ PSU_SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
- Post or pre or main DP path selection
- (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U)
- RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 );
+ Enable force on enable Spread Spectrum
+ (OFFSET, MASK, VALUE) (0XFD40237C, 0x00000033U ,0x00000030U)
+ RegMask = (SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
- | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+ RegVal = ((0x00000000U << SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+ | 0x00000001U << SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+ | 0x00000001U << SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
+ PSU_Mask_Write (SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
/*############################################################################################################################ */
- /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8</p>
+ /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370</p>
- Test register force for enabling/disablign TX deemphasis bits <17:0>
- PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+ Step Size for Spread Spectrum [7:0]
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
- Enable Override of TX deemphasis
- (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
+ Step Size for Spread Spectrum LSB
+ (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU)
+ RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+ RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU);
/*############################################################################################################################ */
- /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8</p>
+ /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374</p>
- Test register force for enabling/disablign TX deemphasis bits <17:0>
- PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
+ Step Size for Spread Spectrum [15:8]
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
- Enable Override of TX deemphasis
- (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U)
- RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
+ Step Size for Spread Spectrum 1
+ (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U)
+ RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+ RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U);
/*############################################################################################################################ */
- // : CDR AND RX EQUALIZATION SETTINGS
- /*Register : L3_TM_CDR5 @ 0XFD40DC14</p>
-
- FPHL FSM accumulate cycles
- PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7
+ /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378</p>
- FFL Phase0 int gain aka 2ol SD update rate
- PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6
+ Step Size for Spread Spectrum [23:16]
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
- Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control.
- (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U)
- RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK | 0 );
+ Step Size for Spread Spectrum 2
+ (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U)
+ RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
- RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
- | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
+ RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
/*############################################################################################################################ */
- /*Register : L3_TM_CDR16 @ 0XFD40DC40</p>
+ /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C</p>
- FFL Phase0 prop gain aka 1ol SD update rate
- PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC
+ Step Size for Spread Spectrum [25:24]
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
- Fast phase lock controls -- phase 0 prop gain
- (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU)
- RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK | 0 );
+ Enable/Disable test mode force on SS step size
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
- RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
+ Enable/Disable test mode force on SS no of steps
+ PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
+
+ Enable force on enable Spread Spectrum
+ (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U)
+ RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+ | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+ | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU);
+ PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
/*############################################################################################################################ */
- /*Register : L3_TM_EQ0 @ 0XFD40D94C</p>
+ /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370</p>
- EQ stg 2 controls BYPASSED
- PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1
+ Step Size for Spread Spectrum [7:0]
+ PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4
- eq stg1 and stg2 controls
- (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U)
- RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK | 0 );
+ Step Size for Spread Spectrum LSB
+ (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U)
+ RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
+ RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U);
+ PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U);
/*############################################################################################################################ */
- /*Register : L3_TM_EQ1 @ 0XFD40D950</p>
-
- EQ STG2 RL PROG
- PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2
+ /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374</p>
- EQ stg 2 preamp mode val
- PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1
+ Step Size for Spread Spectrum [15:8]
+ PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31
- eq stg1 and stg2 controls
- (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U)
- RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK | 0 );
+ Step Size for Spread Spectrum 1
+ (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U)
+ RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
- RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
- | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
+ RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U);
+ PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U);
/*############################################################################################################################ */
- // : GEM SERDES SETTINGS
- // : ENABLE PRE EMPHAIS AND VOLTAGE SWING
- /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0</p>
+ /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378</p>
- Margining factor value
- PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0
+ Step Size for Spread Spectrum [23:16]
+ PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
- Margining factor
- (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U)
- RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK | 0 );
+ Step Size for Spread Spectrum 2
+ (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U)
+ RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
- RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
+ RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
/*############################################################################################################################ */
- /*Register : L1_TX_ANA_TM_18 @ 0XFD404048</p>
+ /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C</p>
- pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
- PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0
+ Step Size for Spread Spectrum [25:24]
+ PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
- Override for PIPE TX de-emphasis
- (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U)
- RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 );
+ Enable/Disable test mode force on SS step size
+ PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
- RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+ Enable/Disable test mode force on SS no of steps
+ PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
+
+ Enable force on enable Spread Spectrum
+ (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U)
+ RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+ | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+ | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
/*############################################################################################################################ */
- /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048</p>
+ /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370</p>
- pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
- PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1
+ Step Size for Spread Spectrum [7:0]
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9
- Override for PIPE TX de-emphasis
- (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U)
- RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 );
+ Step Size for Spread Spectrum LSB
+ (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U)
+ RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+ RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U);
/*############################################################################################################################ */
- // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG,CDR_LOCK_TIME
- /*Register : L0_TM_RST_DLY @ 0XFD4019A4</p>
+ /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374</p>
- Delay apb reset by specified amount
- PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF
+ Step Size for Spread Spectrum [15:8]
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2
- reset delay for apb reset w.r.t pso of hsrx
- (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU)
- RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+ Step Size for Spread Spectrum 1
+ (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U)
+ RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 );
- RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
+ RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U);
/*############################################################################################################################ */
- /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038</p>
+ /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378</p>
- Enable Bypass for <7> of TM_ANA_BYPS_15
- PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+ Step Size for Spread Spectrum [23:16]
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1
- Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
- (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U)
- RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+ Step Size for Spread Spectrum 2
+ (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U)
+ RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U);
/*############################################################################################################################ */
- /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C</p>
+ /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C</p>
- Enable Bypass for <7> of TM_ANA_BYPS_12
- PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+ Step Size for Spread Spectrum [25:24]
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
- Enable Bypass for <5> of TM_ANA_BYPS_12
- PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES 0x1
+ Enable/Disable test mode force on SS step size
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
- Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
- (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000050U ,0x00000050U)
- RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK | 0 );
+ Enable/Disable test mode force on SS no of steps
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
- RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
- | 0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT
+ Enable test mode forcing on enable Spread Spectrum
+ PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1
+
+ Enable force on enable Spread Spectrum
+ (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U)
+ RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK | 0 );
+
+ RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+ | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+ | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+ | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000050U ,0x00000050U);
+ PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U);
/*############################################################################################################################ */
- /*Register : L0_TM_DIG_21 @ 0XFD4010A8</p>
+ /*Register : L2_TM_DIG_6 @ 0XFD40906C</p>
- pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20
- PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11
+ Bypass Descrambler
+ PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1
- pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20
- PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11
+ Enable Bypass for <1> TM_DIG_CTRL_6
+ PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
- Control symbol alignment locking - wait counts
- (OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U)
- RegMask = (SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 );
+ Data path test modes in decoder and descram
+ (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U)
+ RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 );
- RegVal = ((0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
- | 0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
+ | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U);
+ PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U);
/*############################################################################################################################ */
- /*Register : L0_TM_DIG_10 @ 0XFD40107C</p>
+ /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4</p>
+
+ Bypass scrambler signal
+ PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1
- CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
- PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF
+ Enable/disable scrambler bypass signal
+ PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
- test control for changing cdr lock wait time
- (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU)
- RegMask = (SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 );
+ MPHY PLL Gear and bypass scrambler
+ (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U)
+ RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 );
- RegVal = ((0x0000000FU << SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
+ | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L0_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU);
+ PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U);
/*############################################################################################################################ */
- /*Register : L1_TM_RST_DLY @ 0XFD4059A4</p>
+ /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360</p>
- Delay apb reset by specified amount
- PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF
+ Enable test mode force on fractional mode enable
+ PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1
- reset delay for apb reset w.r.t pso of hsrx
- (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU)
- RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+ Fractional feedback division control and fractional value for feedback division bits 26:24
+ (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK | 0 );
- RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038</p>
-
- Enable Bypass for <7> of TM_ANA_BYPS_15
- PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
-
- Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
- (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U)
- RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+ /*Register : L3_TM_DIG_6 @ 0XFD40D06C</p>
- RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
- /*############################################################################################################################ */
+ Bypass 8b10b decoder
+ PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1
- /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C</p>
+ Enable Bypass for <3> TM_DIG_CTRL_6
+ PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1
- Enable Bypass for <7> of TM_ANA_BYPS_12
- PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+ Bypass Descrambler
+ PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1
- Enable Bypass for <5> of TM_ANA_BYPS_12
- PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES 0x1
+ Enable Bypass for <1> TM_DIG_CTRL_6
+ PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
- Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
- (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000050U ,0x00000050U)
- RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK | 0 );
+ Data path test modes in decoder and descram
+ (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU)
+ RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
- | 0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
+ | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
+ | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
+ | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000050U ,0x00000050U);
+ PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU);
/*############################################################################################################################ */
- /*Register : L1_TM_DIG_21 @ 0XFD4050A8</p>
+ /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4</p>
+
+ Enable/disable encoder bypass signal
+ PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1
+
+ Bypass scrambler signal
+ PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1
- pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20
- PSU_SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11
+ Enable/disable scrambler bypass signal
+ PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
- Control symbol alignment locking - wait counts
- (OFFSET, MASK, VALUE) (0XFD4050A8, 0x00000003U ,0x00000003U)
- RegMask = (SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 );
+ MPHY PLL Gear and bypass scrambler
+ (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU)
+ RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 );
- RegVal = ((0x00000011U << SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
+ | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
+ | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U);
+ PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU);
/*############################################################################################################################ */
- /*Register : L1_TM_DIG_10 @ 0XFD40507C</p>
+ /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00</p>
- CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
- PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF
+ PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
+ PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21
- test control for changing cdr lock wait time
- (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x0000000FU)
- RegMask = (SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 );
+ Opmode Info
+ (OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U)
+ RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK | 0 );
- RegVal = ((0x0000000FU << SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+ RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L1_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU);
+ PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
/*############################################################################################################################ */
- /*Register : L2_TM_RST_DLY @ 0XFD4099A4</p>
+ // : ENABLE CHICKEN BIT FOR PCIE AND USB
+ /*Register : L2_TM_AUX_0 @ 0XFD4090CC</p>
- Delay apb reset by specified amount
- PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF
+ Spare- not used
+ PSU_SERDES_L2_TM_AUX_0_BIT_2 1
- reset delay for apb reset w.r.t pso of hsrx
- (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU)
- RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+ Spare registers
+ (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U)
+ RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK | 0 );
- RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U);
/*############################################################################################################################ */
- /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038</p>
+ // : ENABLING EYE SURF
+ /*Register : L0_TM_DIG_8 @ 0XFD401074</p>
- Enable Bypass for <7> of TM_ANA_BYPS_15
- PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+ Enable Eye Surf
+ PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1
- Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
- (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U)
- RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
/*############################################################################################################################ */
- /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C</p>
-
- Enable Bypass for <7> of TM_ANA_BYPS_12
- PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+ /*Register : L1_TM_DIG_8 @ 0XFD405074</p>
- Enable Bypass for <5> of TM_ANA_BYPS_12
- PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES 0x1
+ Enable Eye Surf
+ PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1
- Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
- (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000050U ,0x00000050U)
- RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK | 0 );
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
- | 0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT
+ RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000050U ,0x00000050U);
+ PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
/*############################################################################################################################ */
- /*Register : L2_TM_DIG_21 @ 0XFD4090A8</p>
+ /*Register : L2_TM_DIG_8 @ 0XFD409074</p>
- pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20
- PSU_SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11
+ Enable Eye Surf
+ PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1
- Control symbol alignment locking - wait counts
- (OFFSET, MASK, VALUE) (0XFD4090A8, 0x00000003U ,0x00000003U)
- RegMask = (SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 );
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
- RegVal = ((0x00000011U << SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U);
+ PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
/*############################################################################################################################ */
- /*Register : L2_TM_DIG_10 @ 0XFD40907C</p>
+ /*Register : L3_TM_DIG_8 @ 0XFD40D074</p>
- CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
- PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF
+ Enable Eye Surf
+ PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1
- test control for changing cdr lock wait time
- (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x0000000FU)
- RegMask = (SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 );
+ Test modes for Elastic buffer and enabling Eye Surf
+ (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U)
+ RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK | 0 );
- RegVal = ((0x0000000FU << SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L2_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU);
+ PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U);
/*############################################################################################################################ */
- /*Register : L3_TM_RST_DLY @ 0XFD40D9A4</p>
+ // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS
+ /*Register : L2_TM_MISC2 @ 0XFD40989C</p>
- Delay apb reset by specified amount
- PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF
+ ILL calib counts BYPASSED with calcode bits
+ PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
- reset delay for apb reset w.r.t pso of hsrx
- (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU)
- RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+ sampler cal
+ (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
- RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
+ PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
/*############################################################################################################################ */
- /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038</p>
+ /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8</p>
- Enable Bypass for <7> of TM_ANA_BYPS_15
- PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+ IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A
- Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
- (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U)
- RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU);
/*############################################################################################################################ */
- /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C</p>
-
- Enable Bypass for <7> of TM_ANA_BYPS_12
- PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
+ /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC</p>
- Enable Bypass for <5> of TM_ANA_BYPS_12
- PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES 0x1
+ IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A
- Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
- (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000050U ,0x00000050U)
- RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK | 0 );
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
- RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
- | 0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000050U ,0x00000050U);
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU);
/*############################################################################################################################ */
- /*Register : L3_TM_DIG_10 @ 0XFD40D07C</p>
+ /*Register : L2_TM_ILL12 @ 0XFD409990</p>
- CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
- PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF
+ G1A pll ctr bypass value
+ PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10
- test control for changing cdr lock wait time
- (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x0000000FU)
- RegMask = (SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 );
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U)
+ RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
- RegVal = ((0x0000000FU << SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+ RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SERDES_L3_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU);
+ PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U);
/*############################################################################################################################ */
+ /*Register : L2_TM_E_ILL1 @ 0XFD409924</p>
- return 1;
-}
-unsigned long psu_resetout_init_data() {
- // : TAKING SERDES PERIPHERAL OUT OF RESET RESET
- // : PUTTING USB0 IN RESET
- /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
-
- USB 0 reset for control registers
- PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0
+ E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE
- Software control register for the LPD block.
- (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U)
- RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | 0 );
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU)
+ RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
- RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+ RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU);
/*############################################################################################################################ */
- // : USB0 PIPE POWER PRESENT
- /*Register : fpd_power_prsnt @ 0XFF9D0080</p>
+ /*Register : L2_TM_E_ILL2 @ 0XFD409928</p>
- This bit is used to choose between PIPE power present and 1'b1
- PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1
+ E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0
- fpd_power_prsnt
- (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U)
- RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK | 0 );
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
- RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
+ RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U);
/*############################################################################################################################ */
- // :
- /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
-
- USB 0 sleep circuit reset
- PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0
+ /*Register : L2_TM_IQ_ILL3 @ 0XFD409900</p>
- USB 0 reset
- PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0
+ IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A
- Software control register for the LPD block.
- (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U)
- RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 );
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU)
+ RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
- RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
- | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+ RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU);
/*############################################################################################################################ */
- // : PUTTING USB1 IN RESET
- /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
+ /*Register : L2_TM_E_ILL3 @ 0XFD40992C</p>
- USB 1 reset for control registers
- PSU_CRL_APB_RST_LPD_TOP_USB1_APB_RESET 0X0
+ E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
- Software control register for the LPD block.
- (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000800U ,0x00000000U)
- RegMask = (CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK | 0 );
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
- RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT
+ RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000800U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U);
/*############################################################################################################################ */
- // : USB1 PIPE POWER PRESENT
- /*Register : fpd_power_prsnt @ 0XFF9E0080</p>
+ /*Register : L2_TM_ILL8 @ 0XFD409980</p>
- This bit is used to choose between PIPE power present and 1'b1
- PSU_USB3_1_FPD_POWER_PRSNT_OPTION 0X1
+ ILL calibration code change wait time
+ PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
- fpd_power_prsnt
- (OFFSET, MASK, VALUE) (0XFF9E0080, 0x00000001U ,0x00000001U)
- RegMask = (USB3_1_FPD_POWER_PRSNT_OPTION_MASK | 0 );
+ ILL cal routine control
+ (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
- RegVal = ((0x00000001U << USB3_1_FPD_POWER_PRSNT_OPTION_SHIFT
+ RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (USB3_1_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
+ PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
/*############################################################################################################################ */
- // :
- /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
-
- USB 1 sleep circuit reset
- PSU_CRL_APB_RST_LPD_TOP_USB1_HIBERRESET 0X0
+ /*Register : L2_TM_IQ_ILL8 @ 0XFD409914</p>
- USB 1 reset
- PSU_CRL_APB_RST_LPD_TOP_USB1_CORERESET 0X0
+ IQ ILL polytrim bypass value
+ PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
- Software control register for the LPD block.
- (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000280U ,0x00000000U)
- RegMask = (CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK | 0 );
+ iqpi polytrim
+ (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
- RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT
- | 0x00000000U << CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT
+ RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000280U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
/*############################################################################################################################ */
- // : PUTTING GEM0 IN RESET
- /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
+ /*Register : L2_TM_IQ_ILL9 @ 0XFD409918</p>
- GEM 3 reset
- PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0
+ bypass IQ polytrim
+ PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
- Software controlled reset for the GEMs
- (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U)
- RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 );
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
- RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- // : PUTTING SATA IN RESET
- /*Register : sata_misc_ctrl @ 0XFD3D0100</p>
+ /*Register : L2_TM_E_ILL8 @ 0XFD409940</p>
- Sata PM clock control select
- PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3
+ E ILL polytrim bypass value
+ PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
- Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
- (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U)
- RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK | 0 );
+ epi polytrim
+ (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
- RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
+ RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U);
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
/*############################################################################################################################ */
- /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
+ /*Register : L2_TM_E_ILL9 @ 0XFD409944</p>
- Sata block level reset
- PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0
+ bypass E polytrim
+ PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
- FPD Block level software controlled reset
- (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U)
- RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 );
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
- RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- // : PUTTING PCIE CFG AND BRIDGE IN RESET
- /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
-
- PCIE config reset
- PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0
+ /*Register : L3_TM_MISC2 @ 0XFD40D89C</p>
- PCIE bridge block level reset (AXI interface)
- PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0
+ ILL calib counts BYPASSED with calcode bits
+ PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
- FPD Block level software controlled reset
- (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U)
- RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 );
+ sampler cal
+ (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U)
+ RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 );
- RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
- | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000C0000U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U);
/*############################################################################################################################ */
- // : PUTTING DP IN RESET
- /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
+ /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8</p>
- Display Port block level reset (includes DPDMA)
- PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0
+ IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D
- FPD Block level software controlled reset
- (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U)
- RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 );
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 );
- RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU);
/*############################################################################################################################ */
- /*Register : DP_PHY_RESET @ 0XFD4A0200</p>
+ /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC</p>
- Set to '1' to hold the GT in reset. Clear to release.
- PSU_DP_DP_PHY_RESET_GT_RESET 0X0
+ IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D
- Reset the transmitter PHY.
- (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U)
- RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 );
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 );
- RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU);
/*############################################################################################################################ */
- /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
+ /*Register : L3_TM_ILL12 @ 0XFD40D990</p>
- Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
- ane0 Bits [3:2] - lane 1
- PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0
+ G1A pll ctr bypass value
+ PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1
- Control PHY Power down
- (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U)
- RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 );
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U)
+ RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 );
- RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U);
/*############################################################################################################################ */
- // : USB0 GFLADJ
- /*Register : GUSB2PHYCFG @ 0XFE20C200</p>
+ /*Register : L3_TM_E_ILL1 @ 0XFD40D924</p>
- USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
- he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
- C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
- . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
- UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
- alue. Note: This field is valid only in device mode.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0X9
+ E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS
+ PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C
- Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
- of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
- time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
- ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
- off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
- ng hibernation. - This bit is valid only in device mode.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0X0
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU)
+ RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 );
- Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
- _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
- to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
- ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
- n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
- d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
- d.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0X0
+ RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU);
+ /*############################################################################################################################ */
- USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
- Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
- 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
- in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
- active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0X0
+ /*Register : L3_TM_E_ILL2 @ 0XFD40D928</p>
- Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0X1
+ E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
+ PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39
- Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
- full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
- ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
- B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0X0
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U)
+ RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 );
- ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
- e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
- ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
- lected through DWC_USB3_HSPHY_INTERFACE.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0X1
+ RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U);
+ /*############################################################################################################################ */
- PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
- 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
- lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
- ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
- any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
- PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0X0
+ /*Register : L3_TM_ILL11 @ 0XFD40D98C</p>
- HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
- a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
- dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
- e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
- The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
- ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
- clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
- 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
- PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0X7
+ G2A_PCIe1 PLL ctr bypass value
+ PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2
- Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
- he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
- ented.
- (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FFFU ,0x00002457U)
- RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 );
+ ill pll counter values
+ (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U)
+ RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK | 0 );
- RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
- | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
- | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
- | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
- | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
- | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
- | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
- | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
- | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
+ RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FFFU ,0x00002457U);
+ PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U);
/*############################################################################################################################ */
- /*Register : GFLADJ @ 0XFE20C630</p>
-
- This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
- alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
- _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
- TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
- riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
- cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
- uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
- ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
- RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
- PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0X0
+ /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900</p>
- Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
- ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
- to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely
- rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
- (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U)
- RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK | 0 );
+ IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D
- RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
+ iqpi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU)
+ RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 );
+
+ RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU);
/*############################################################################################################################ */
- // : USB1 GFLADJ
- /*Register : GUSB2PHYCFG @ 0XFE30C200</p>
+ /*Register : L3_TM_E_ILL3 @ 0XFD40D92C</p>
- USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
- he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
- C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
- . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
- UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
- alue. Note: This field is valid only in device mode.
- PSU_USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM 0X9
+ E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
+ PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64
- Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
- of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
- time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
- ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
- off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
- ng hibernation. - This bit is valid only in device mode.
- PSU_USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY 0X0
+ epi cal code
+ (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U)
+ RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 );
- Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
- _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
- to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
- ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
- n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
- d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
- d.
- PSU_USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM 0X0
+ RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U);
+ /*############################################################################################################################ */
- USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
- Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
- 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
- in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
- active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
- PSU_USB3_1_XHCI_GUSB2PHYCFG_PHYSEL 0X0
+ /*Register : L3_TM_ILL8 @ 0XFD40D980</p>
- Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
- PSU_USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0X1
+ ILL calibration code change wait time
+ PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
- Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
- full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
- ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
- B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
- PSU_USB3_1_XHCI_GUSB2PHYCFG_FSINTF 0X0
+ ILL cal routine control
+ (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 );
- ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
- e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
- ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
- lected through DWC_USB3_HSPHY_INTERFACE.
- PSU_USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0X1
+ RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU);
+ /*############################################################################################################################ */
- PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
- 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
- lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
- ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
- any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
- PSU_USB3_1_XHCI_GUSB2PHYCFG_PHYIF 0X0
+ /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914</p>
- HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
- a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
- dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
- e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
- The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
- ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
- clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
- 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
- PSU_USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL 0X7
+ IQ ILL polytrim bypass value
+ PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
- Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
- he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
- ented.
- (OFFSET, MASK, VALUE) (0XFE30C200, 0x00003FFFU ,0x00002457U)
- RegMask = (USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_1_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK | USB3_1_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_1_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 );
+ iqpi polytrim
+ (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 );
- RegVal = ((0x00000009U << USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
- | 0x00000000U << USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
- | 0x00000000U << USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
- | 0x00000000U << USB3_1_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
- | 0x00000001U << USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
- | 0x00000000U << USB3_1_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
- | 0x00000001U << USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
- | 0x00000000U << USB3_1_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
- | 0x00000007U << USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
+ RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (USB3_1_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FFFU ,0x00002457U);
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
/*############################################################################################################################ */
- /*Register : GFLADJ @ 0XFE30C630</p>
+ /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918</p>
- This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
- alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
- _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
- TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
- riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
- cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
- uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
- ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
- RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
- PSU_USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0X0
+ bypass IQ polytrim
+ PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
- Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
- ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
- to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely
- rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
- (OFFSET, MASK, VALUE) (0XFE30C630, 0x003FFF00U ,0x00000000U)
- RegMask = (USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK | 0 );
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 );
- RegVal = ((0x00000000U << USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (USB3_1_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- // : CHECK PLL LOCK FOR LANE0
- /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4</p>
+ /*Register : L3_TM_E_ILL8 @ 0XFD40D940</p>
- Status Read value of PLL Lock
- PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+ E ILL polytrim bypass value
+ PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
+
+ epi polytrim
+ (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U)
+ RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 );
+ RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U);
/*############################################################################################################################ */
- // : CHECK PLL LOCK FOR LANE1
- /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4</p>
+ /*Register : L3_TM_E_ILL9 @ 0XFD40D944</p>
- Status Read value of PLL Lock
- PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+ bypass E polytrim
+ PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
+
+ enables for lf,constant gm trim and polytirm
+ (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 );
+ RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- // : CHECK PLL LOCK FOR LANE2
- /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4</p>
+ // : SYMBOL LOCK AND WAIT
+ // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
+ /*Register : L0_TM_RST_DLY @ 0XFD4019A4</p>
- Status Read value of PLL Lock
- PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+ Delay apb reset by specified amount
+ PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF
+
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
+ RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
/*############################################################################################################################ */
- // : CHECK PLL LOCK FOR LANE3
- /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4</p>
+ /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038</p>
- Status Read value of PLL Lock
- PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
- (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */
- mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
+
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
+ RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
- /*Register : ATTR_25 @ 0XFD480064</p>
+ /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C</p>
- If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
- ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
- ATTR_25
- (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U)
- RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK | 0 );
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
+ RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U);
+ PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- // : PCIE SETTINGS
- /*Register : ATTR_7 @ 0XFD48001C</p>
+ /*Register : L1_TM_RST_DLY @ 0XFD4059A4</p>
- Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
- ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
- Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
- erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
- set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
- re size in bytes.; EP=0x0004; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0
+ Delay apb reset by specified amount
+ PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF
- ATTR_7
- (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK | 0 );
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
+ RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
/*############################################################################################################################ */
- /*Register : ATTR_8 @ 0XFD480020</p>
+ /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038</p>
- Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
- ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
- Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
- erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
- set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
- re size in bytes.; EP=0xFFF0; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
- ATTR_8
- (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK | 0 );
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
+ RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- /*Register : ATTR_9 @ 0XFD480024</p>
+ /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C</p>
- Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
- AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
- bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
- o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
- 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
- '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
- ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
- ATTR_9
- (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK | 0 );
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
+ RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- /*Register : ATTR_10 @ 0XFD480028</p>
+ /*Register : L2_TM_RST_DLY @ 0XFD4099A4</p>
- Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
- AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
- bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
- o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
- 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
- '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
- ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0
+ Delay apb reset by specified amount
+ PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF
- ATTR_10
- (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK | 0 );
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
+ RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
/*############################################################################################################################ */
- /*Register : ATTR_11 @ 0XFD48002C</p>
+ /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038</p>
- For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
- AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
- , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
- ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
- most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
- . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
- ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF
- PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
- ATTR_11
- (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU)
- RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK | 0 );
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
- RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
+ PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- /*Register : ATTR_12 @ 0XFD480030</p>
+ /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C</p>
- For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
- AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
- , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
- ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
- most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
- . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
- ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF
- PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
- ATTR_12
- (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU)
- RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK | 0 );
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
- RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
+ RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU);
+ PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- /*Register : ATTR_13 @ 0XFD480034</p>
+ /*Register : L3_TM_RST_DLY @ 0XFD40D9A4</p>
- For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
- AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
- Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
- t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
- t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
- if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
- f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
- bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0
+ Delay apb reset by specified amount
+ PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF
- ATTR_13
- (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK | 0 );
+ reset delay for apb reset w.r.t pso of hsrx
+ (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU)
+ RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
+ RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU);
/*############################################################################################################################ */
- /*Register : ATTR_14 @ 0XFD480038</p>
+ /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038</p>
- For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
- AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
- Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
- t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
- t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
- if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
- f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
- bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF
- PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF
+ Enable Bypass for <7> of TM_ANA_BYPS_15
+ PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
- ATTR_14
- (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU)
- RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK | 0 );
+ Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c
+ (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 );
- RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
+ PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- /*Register : ATTR_15 @ 0XFD48003C</p>
+ /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C</p>
- For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
- AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
- , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
- ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
- most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
- . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
- ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0
- PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0
+ Enable Bypass for <7> of TM_ANA_BYPS_12
+ PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
- ATTR_15
- (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U)
- RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK | 0 );
+ Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls
+ (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U)
+ RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 );
- RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
+ PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U);
/*############################################################################################################################ */
- /*Register : ATTR_16 @ 0XFD480040</p>
+ // : GT LANE SETTINGS
+ /*Register : ICM_CFG0 @ 0XFD410010</p>
+
+ Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
+ , 7 - Unused
+ PSU_SERDES_ICM_CFG0_L0_ICM_CFG 4
- For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
- AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
- , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
- ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
- most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
- . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
- ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0
- PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0
+ Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
+ 7 - Unused
+ PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4
- ATTR_16
- (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U)
- RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK | 0 );
+ ICM Configuration Register 0
+ (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000044U)
+ RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK | 0 );
- RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
+ RegVal = ((0x00000004U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
+ | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
+ PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000044U);
/*############################################################################################################################ */
- /*Register : ATTR_17 @ 0XFD480044</p>
+ /*Register : ICM_CFG1 @ 0XFD410014</p>
+
+ Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
+ 7 - Unused
+ PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3
- For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
- AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
- Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
- refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
- R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
- refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
- ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
- permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
- PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1
+ Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
+ 7 - Unused
+ PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2
- ATTR_17
- (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U)
- RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK | 0 );
+ ICM Configuration Register 1
+ (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U)
+ RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK | 0 );
- RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
+ RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
+ | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
+ PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U);
/*############################################################################################################################ */
- /*Register : ATTR_18 @ 0XFD480048</p>
-
- For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
- AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
- Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
- refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
- R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
- refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
- ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
- permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
- PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1
+ // : CHECKING PLL LOCK
+ // : ENABLE SERIAL DATA MUX DEEMPH
+ /*Register : L0_TXPMD_TM_45 @ 0XFD400CB4</p>
- ATTR_18
- (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U)
- RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK | 0 );
+ Enable/disable DP post2 path
+ PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
- RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
- /*############################################################################################################################ */
+ Override enable/disable of DP post2 path
+ PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
- /*Register : ATTR_27 @ 0XFD48006C</p>
+ Override enable/disable of DP post1 path
+ PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
- Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
- to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1
+ Enable/disable DP main path
+ PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
- Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
- state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
- 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0
+ Override enable/disable of DP main path
+ PSU_SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
- ATTR_27
- (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U)
- RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK | 0 );
+ Post or pre or main DP path selection
+ (OFFSET, MASK, VALUE) (0XFD400CB4, 0x00000037U ,0x00000037U)
+ RegMask = (SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 );
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
- | 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
+ RegVal = ((0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+ | 0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+ | 0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+ | 0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+ | 0x00000001U << SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U);
+ PSU_Mask_Write (SERDES_L0_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
/*############################################################################################################################ */
- /*Register : ATTR_50 @ 0XFD4800C8</p>
-
- Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
- 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
- tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
- gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004
- PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4
+ /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4</p>
- PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
- lity.; EP=0x009C; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0
+ Enable/disable DP post2 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
- ATTR_50
- (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U)
- RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK | 0 );
+ Override enable/disable of DP post2 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
- RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
- | 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U);
- /*############################################################################################################################ */
+ Override enable/disable of DP post1 path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
- /*Register : ATTR_105 @ 0XFD4801A4</p>
+ Enable/disable DP main path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
- Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
- ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
- PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD
+ Override enable/disable of DP main path
+ PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
- ATTR_105
- (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU)
- RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK | 0 );
+ Post or pre or main DP path selection
+ (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U)
+ RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 );
- RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
+ RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+ | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU);
+ PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
/*############################################################################################################################ */
- /*Register : ATTR_106 @ 0XFD4801A8</p>
+ /*Register : L0_TX_ANA_TM_118 @ 0XFD4001D8</p>
- Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non
- osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024
- PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24
-
- Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
- a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
- completion header credits must be <= 80; EP=0x0004; RP=0x000C
- PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC
+ Test register force for enabling/disablign TX deemphasis bits <17:0>
+ PSU_SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
- ATTR_106
- (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U)
- RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK | 0 );
+ Enable Override of TX deemphasis
+ (OFFSET, MASK, VALUE) (0XFD4001D8, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
- RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
- | 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
+ RegVal = ((0x00000001U << SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U);
+ PSU_Mask_Write (SERDES_L0_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- /*Register : ATTR_107 @ 0XFD4801AC</p>
+ /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8</p>
- Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data
- redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
- d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
- less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
- PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18
+ Test register force for enabling/disablign TX deemphasis bits <17:0>
+ PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
- ATTR_107
- (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U)
- RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK | 0 );
+ Enable Override of TX deemphasis
+ (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
- RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
+ RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U);
+ PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- /*Register : ATTR_108 @ 0XFD4801B0</p>
+ /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8</p>
- Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less
- han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
- PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5
+ Test register force for enabling/disablign TX deemphasis bits <17:0>
+ PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
- ATTR_108
- (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U)
- RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK | 0 );
+ Enable Override of TX deemphasis
+ (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U)
+ RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 );
- RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U);
+ PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- /*Register : ATTR_109 @ 0XFD4801B4</p>
-
- Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
- 0
- PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0
-
- Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1
-
- Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
- cap structure; EP=0x0003; RP=0x0003
- PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3
+ // : CDR AND RX EQUALIZATION SETTINGS
+ /*Register : L3_TM_CDR5 @ 0XFD40DC14</p>
- Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
- mber of brams configured for transmit; EP=0x001C; RP=0x001C
- PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c
+ FPHL FSM accumulate cycles
+ PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7
- Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
- d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020
- PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20
+ FFL Phase0 int gain aka 2ol SD update rate
+ PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6
- ATTR_109
- (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U)
- RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK | 0 );
+ Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control.
+ (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U)
+ RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
- | 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
- | 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
- | 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
- | 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
+ RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
+ | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U);
+ PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U);
/*############################################################################################################################ */
- /*Register : ATTR_34 @ 0XFD480088</p>
+ /*Register : L3_TM_CDR16 @ 0XFD40DC40</p>
- Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
- 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1
+ FFL Phase0 prop gain aka 1ol SD update rate
+ PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC
- ATTR_34
- (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U)
- RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK | 0 );
+ Fast phase lock controls -- phase 0 prop gain
+ (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU)
+ RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK | 0 );
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
+ RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U);
+ PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU);
/*############################################################################################################################ */
- /*Register : ATTR_53 @ 0XFD4800D4</p>
+ /*Register : L3_TM_EQ0 @ 0XFD40D94C</p>
- PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
- ty.; EP=0x0048; RP=0x0060
- PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60
+ EQ stg 2 controls BYPASSED
+ PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1
- ATTR_53
- (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U)
- RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK | 0 );
+ eq stg1 and stg2 controls
+ (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U)
+ RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK | 0 );
- RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U);
+ PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U);
/*############################################################################################################################ */
- /*Register : ATTR_41 @ 0XFD4800A4</p>
-
- MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
- to Cap structure; EP=0x0000; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0
-
- Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
- he management port.; EP=0x0001; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
+ /*Register : L3_TM_EQ1 @ 0XFD40D950</p>
- MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
- ity.; EP=0x0060; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0
+ EQ STG2 RL PROG
+ PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2
- Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
- he management port.; EP=0x0001; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
+ EQ stg 2 preamp mode val
+ PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1
- ATTR_41
- (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | 0 );
+ eq stg1 and stg2 controls
+ (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U)
+ RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
- | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
- | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
- | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
+ RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
+ | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U);
+ PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U);
/*############################################################################################################################ */
- /*Register : ATTR_97 @ 0XFD480184</p>
-
- Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004
- PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1
+ // : GEM SERDES SETTINGS
+ // : ENABLE PRE EMPHAIS AND VOLTAGE SWING
+ /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0</p>
- Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
- 4; RP=0x0004
- PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1
+ Margining factor value
+ PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0
- ATTR_97
- (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U)
- RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK | 0 );
+ Margining factor
+ (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U)
+ RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK | 0 );
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
- | 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
+ RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U);
+ PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_100 @ 0XFD480190</p>
+ /*Register : L0_TXPMD_TM_48 @ 0XFD400CC0</p>
- TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0
+ Margining factor value
+ PSU_SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0
- ATTR_100
- (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK | 0 );
+ Margining factor
+ (OFFSET, MASK, VALUE) (0XFD400CC0, 0x0000001FU ,0x00000000U)
+ RegMask = (SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
+ RegVal = ((0x00000000U << SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U);
+ PSU_Mask_Write (SERDES_L0_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_101 @ 0XFD480194</p>
-
- Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message
- LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
- Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
- EP=0x0000; RP=0x07FF
- PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF
+ /*Register : L1_TX_ANA_TM_18 @ 0XFD404048</p>
- Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1
+ pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+ PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0
- ATTR_101
- (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U)
- RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK | 0 );
+ Override for PIPE TX de-emphasis
+ (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 );
- RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
- | 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
+ RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U);
+ PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_37 @ 0XFD480094</p>
-
- Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
- Required for Root.; EP=0x0000; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1
+ /*Register : L0_TX_ANA_TM_18 @ 0XFD400048</p>
- Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
- gister.; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1
+ pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+ PSU_SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0
- ATTR_37
- (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U)
- RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 );
+ Override for PIPE TX de-emphasis
+ (OFFSET, MASK, VALUE) (0XFD400048, 0x000000FFU ,0x00000000U)
+ RegMask = (SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 );
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
- | 0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
+ RegVal = ((0x00000000U << SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004200U ,0x00004200U);
+ PSU_Mask_Write (SERDES_L0_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_93 @ 0XFD480174</p>
-
- Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
- _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1
+ /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048</p>
- Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
- TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
- 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000
+ pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+ PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1
- ATTR_93
- (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U)
- RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK | 0 );
+ Override for PIPE TX de-emphasis
+ (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U)
+ RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 );
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
- | 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
+ RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U);
+ PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U);
/*############################################################################################################################ */
- /*Register : ID @ 0XFD480200</p>
- Device ID for the the PCIe Cap Structure Device ID field
- PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021
+ return 1;
+}
+unsigned long psu_resetout_init_data() {
+ // : TAKING SERDES PERIPHERAL OUT OF RESET RESET
+ // : PUTTING USB0 IN RESET
+ /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
- Vendor ID for the PCIe Cap Structure Vendor ID field
- PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee
+ USB 0 reset for control registers
+ PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0
- ID
- (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U)
- RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK | 0 );
+ Software control register for the LPD block.
+ (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U)
+ RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | 0 );
- RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
- | 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
+ RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U);
+ PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : SUBSYS_ID @ 0XFD480204</p>
-
- Subsystem ID for the the PCIe Cap Structure Subsystem ID field
- PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7
+ // : USB0 PIPE POWER PRESENT
+ /*Register : fpd_power_prsnt @ 0XFF9D0080</p>
- Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
- PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee
+ This bit is used to choose between PIPE power present and 1'b1
+ PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1
- SUBSYS_ID
- (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U)
- RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK | 0 );
+ fpd_power_prsnt
+ (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U)
+ RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK | 0 );
- RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
- | 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
+ RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U);
+ PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
/*############################################################################################################################ */
- /*Register : REV_ID @ 0XFD480208</p>
+ /*Register : fpd_pipe_clk @ 0XFF9D007C</p>
- Revision ID for the the PCIe Cap Structure
- PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0
+ This bit is used to choose between PIPE clock coming from SerDes and the suspend clk
+ PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0
- REV_ID
- (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK | 0 );
+ fpd_pipe_clk
+ (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U)
+ RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
+ RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U);
+ PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_24 @ 0XFD480060</p>
+ // :
+ /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
+
+ USB 0 sleep circuit reset
+ PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0
- Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
- 8000; RP=0x8000
- PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400
+ USB 0 reset
+ PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0
- ATTR_24
- (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U)
- RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK | 0 );
+ Software control register for the LPD block.
+ (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U)
+ RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 );
- RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
+ RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+ | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U);
+ PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_25 @ 0XFD480064</p>
-
- Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
- 0005; RP=0x0006
- PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6
+ // : PUTTING GEM0 IN RESET
+ /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
- INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0
+ GEM 3 reset
+ PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0
- ATTR_25
- (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U)
- RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK | 0 );
+ Software controlled reset for the GEMs
+ (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U)
+ RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 );
- RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
- | 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
+ RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U);
+ PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_0 @ 0XFD480000</p>
+ // : PUTTING SATA IN RESET
+ /*Register : sata_misc_ctrl @ 0XFD3D0100</p>
- Indicates that the core is capable of generating ECRC. Value transferred to bit 5 of the AER Capabilities and Control Registe
- .; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE 0
+ Sata PM clock control select
+ PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3
- ATTR_0
- (OFFSET, MASK, VALUE) (0XFD480000, 0x00000002U ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE_MASK | 0 );
+ Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
+ (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U)
+ RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE_SHIFT
+ RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_0_OFFSET ,0x00000002U ,0x00000000U);
+ PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U);
/*############################################################################################################################ */
- /*Register : ATTR_4 @ 0XFD480010</p>
-
- Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
- he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
- ges are sent if an error is detected).; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
+ /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
- Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
- he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
- ges are sent if an error is detected).; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
+ Sata block level reset
+ PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0
- ATTR_4
- (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | 0 );
+ FPD Block level software controlled reset
+ (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U)
+ RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
- | 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
+ RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U);
+ PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_89 @ 0XFD480164</p>
+ // : PUTTING DP IN RESET
+ /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
- VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
- 0x0140; RP=0x0140
- PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0
+ Display Port block level reset (includes DPDMA)
+ PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0
- ATTR_89
- (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK | 0 );
+ FPD Block level software controlled reset
+ (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U)
+ RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
+ RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U);
+ PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_79 @ 0XFD48013C</p>
+ /*Register : DP_PHY_RESET @ 0XFD4A0200</p>
- CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1
+ Set to '1' to hold the GT in reset. Clear to release.
+ PSU_DP_DP_PHY_RESET_GT_RESET 0X0
- ATTR_79
- (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U)
- RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK | 0 );
+ Reset the transmitter PHY.
+ (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U)
+ RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 );
- RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
+ RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U);
+ PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_43 @ 0XFD4800AC</p>
+ /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
- Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
- the management port.; EP=0x0001; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0
+ Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
+ ane0 Bits [3:2] - lane 1
+ PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0
- ATTR_43
- (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK | 0 );
+ Control PHY Power down
+ (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U)
+ RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
+ RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U);
+ PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_48 @ 0XFD4800C0</p>
-
- MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
- hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0
+ // : USB0 GFLADJ
+ /*Register : GUSB2PHYCFG @ 0XFE20C200</p>
- ATTR_48
- (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK | 0 );
+ USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
+ he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
+ C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
+ . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
+ UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
+ alue. Note: This field is valid only in device mode.
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_48_OFFSET ,0x000007FFU ,0x00000000U);
- /*############################################################################################################################ */
+ Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
+ of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
+ time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
+ ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
+ off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
+ ng hibernation. - This bit is valid only in device mode.
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0
- /*Register : ATTR_46 @ 0XFD4800B8</p>
+ Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
+ _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
+ to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
+ ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
+ n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
+ d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
+ d.
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0
- MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
- P=0x0000
- PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0
+ USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
+ Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
+ 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
+ in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
+ active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0
- ATTR_46
- (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 );
+ Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
+ full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
+ ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
+ B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_46_OFFSET ,0x0000FFFFU ,0x00000000U);
- /*############################################################################################################################ */
+ ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
+ e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
+ ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
+ lected through DWC_USB3_HSPHY_INTERFACE.
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1
- /*Register : ATTR_47 @ 0XFD4800BC</p>
+ PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
+ 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
+ lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
+ ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
+ any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0
- MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
- P=0x0000
- PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0
+ HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
+ a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
+ dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
+ e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
+ The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
+ ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
+ clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
+ 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
+ PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7
- ATTR_47
- (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 );
+ Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
+ he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
+ ented.
+ (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U)
+ RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
+ RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
+ | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
+ | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
+ | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
+ | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
+ | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
+ | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
+ | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_47_OFFSET ,0x00001FFFU ,0x00000000U);
+ PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U);
/*############################################################################################################################ */
- /*Register : ATTR_44 @ 0XFD4800B0</p>
+ /*Register : GFLADJ @ 0XFE20C630</p>
- MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
- 0x0001; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0
+ This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
+ alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
+ _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
+ TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
+ riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
+ cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
+ uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
+ ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
+ RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
+ PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0
- ATTR_44
- (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 );
+ Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
+ ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
+ to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely
+ rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
+ (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U)
+ RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+ RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_44_OFFSET ,0x0000FFFFU ,0x00000000U);
+ PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_45 @ 0XFD4800B4</p>
+ // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
+ /*Register : ATTR_25 @ 0XFD480064</p>
- MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
- 0x1000; RP=0x0000
- PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0
+ If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
+ ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
+ PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1
- ATTR_45
- (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 );
+ ATTR_25
+ (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U)
+ RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK | 0 );
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
+ RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_45_OFFSET ,0x0000FFF8U ,0x00000000U);
+ PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U);
/*############################################################################################################################ */
- /*Register : CB @ 0XFD48031C</p>
-
- DT837748 Enable
- PSU_PCIE_ATTRIB_CB_CB1 0x0
+ // : CHECK PLL LOCK FOR LANE1
+ /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4</p>
- ECO Register 1
- (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U)
- RegMask = (PCIE_ATTRIB_CB_CB1_MASK | 0 );
+ Status Read value of PLL Lock
+ PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
- RegVal = ((0x00000000U << PCIE_ATTRIB_CB_CB1_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_CB_OFFSET ,0x00000002U ,0x00000000U);
/*############################################################################################################################ */
- /*Register : ATTR_35 @ 0XFD48008C</p>
-
- Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
- ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001
- PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0
+ // : CHECK PLL LOCK FOR LANE2
+ /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4</p>
- ATTR_35
- (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U)
- RegMask = (PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK | 0 );
+ Status Read value of PLL Lock
+ PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
- RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (PCIE_ATTRIB_ATTR_35_OFFSET ,0x00003000U ,0x00000000U);
/*############################################################################################################################ */
- // : PUTTING PCIE CONTROL IN RESET
- /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
-
- PCIE control block level reset
- PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
+ // : CHECK PLL LOCK FOR LANE3
+ /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4</p>
- FPD Block level software controlled reset
- (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U)
- RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | 0 );
+ Status Read value of PLL Lock
+ PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
+ (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */
+ mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
- RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00020000U ,0x00000000U);
/*############################################################################################################################ */
// : SATA AHCI VENDOR SETTING
/*Register : PP2C @ 0XFD0C00AC</p>
CIBGMN: COMINIT Burst Gap Minimum.
- PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x1B
+ PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18
CIBGMX: COMINIT Burst Gap Maximum.
- PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x4D
+ PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40
CIBGN: COMINIT Burst Gap Nominal.
PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18
PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete
s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
- (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184D1BU)
+ (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U)
RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK | 0 );
- RegVal = ((0x0000001BU << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
- | 0x0000004DU << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
+ RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
+ | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
| 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
| 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184D1BU);
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U);
/*############################################################################################################################ */
/*Register : PP3C @ 0XFD0C00B0</p>
PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06
CWBGMX: COMWAKE Burst Gap Maximum.
- PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x19
+ PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14
CWBGN: COMWAKE Burst Gap Nominal.
PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08
PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter
for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
- (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081906U)
+ (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U)
RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK | 0 );
RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
- | 0x00000019U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
+ | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
| 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
| 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
| 0 ) & RegMask); */
- PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081906U);
+ PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U);
/*############################################################################################################################ */
/*Register : PP4C @ 0XFD0C00B4</p>
PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U);
/*############################################################################################################################ */
- // : PUTTING USB1 IN RESET
- /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
-
- USB 1 reset for control registers
- PSU_CRL_APB_RST_LPD_TOP_USB1_APB_RESET 0X1
-
- USB 1 sleep circuit reset
- PSU_CRL_APB_RST_LPD_TOP_USB1_HIBERRESET 0X1
-
- USB 1 reset
- PSU_CRL_APB_RST_LPD_TOP_USB1_CORERESET 0X1
-
- Software control register for the LPD block.
- (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000A80U ,0x00000A80U)
- RegMask = (CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK | 0 );
-
- RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT
- | 0x00000001U << CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT
- | 0x00000001U << CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000A80U ,0x00000A80U);
- /*############################################################################################################################ */
-
// : PUTTING GEM0 IN RESET
/*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U);
/*############################################################################################################################ */
- // : PUTTING PCIE IN RESET
- /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
-
- PCIE config reset
- PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1
-
- PCIE control block level reset
- PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1
-
- PCIE bridge block level reset (AXI interface)
- PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1
-
- FPD Block level software controlled reset
- (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U)
- RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 );
-
- RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
- | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
- | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
- | 0 ) & RegMask); */
- PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U);
- /*############################################################################################################################ */
-
// : PUTTING DP IN RESET
/*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
return 1;
}
unsigned long psu_ps_pl_isolation_removal_data() {
+ // : AFI RESET
+ /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
+
+ AF_FM0 block level reset
+ PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0
+
+ AF_FM1 block level reset
+ PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0
+
+ AF_FM2 block level reset
+ PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0
+
+ AF_FM3 block level reset
+ PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0
+
+ AF_FM4 block level reset
+ PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0
+
+ AF_FM5 block level reset
+ PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0
+
+ FPD Block level software controlled reset
+ (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U)
+ RegMask = (CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK | CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK | 0 );
+
+ RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT
+ | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT
+ | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT
+ | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT
+ | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT
+ | 0x00000000U << CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00001F80U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
+
+ AFI FM 6
+ PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0
+
+ Software control register for the LPD block.
+ (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U)
+ RegMask = (CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK | 0 );
+
+ RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00080000U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ // : AFIFM INTERFACE WIDTH
+ /*Register : afi_fs @ 0XFD615000</p>
+
+ Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
+ : 128-bit AXI data width 11: reserved
+ PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2
+
+ Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
+ : 128-bit AXI data width 11: reserved
+ PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2
+
+ afi fs SLCR control register. This register is static and should not be modified during operation.
+ (OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U)
+ RegMask = (FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK | FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK | 0 );
+
+ RegVal = ((0x00000002U << FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT
+ | 0x00000002U << FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (FPD_SLCR_AFI_FS_OFFSET ,0x00000F00U ,0x00000A00U);
+ /*############################################################################################################################ */
+
+ /*Register : afi_fs @ 0XFF419000</p>
+
+ Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
+ : 128-bit AXI data width 11: reserved
+ PSU_LPD_SLCR_AFI_FS_DW_SS2_SEL 0x2
+
+ afi fs SLCR control register. Do not change the bits durin
+ (OFFSET, MASK, VALUE) (0XFF419000, 0x00000300U ,0x00000200U)
+ RegMask = (LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK | 0 );
+
+ RegVal = ((0x00000002U << LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (LPD_SLCR_AFI_FS_OFFSET ,0x00000300U ,0x00000200U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_RDCTRL @ 0XFD360000</p>
+
+ Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled
+ PSU_AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH 0x0
+
+ Read Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD360000, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM0_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_RDCTRL @ 0XFD370000</p>
+
+ Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled
+ PSU_AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH 0x0
+
+ Read Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD370000, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM1_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_RDCTRL @ 0XFD380000</p>
+
+ Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled
+ PSU_AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH 0x0
+
+ Read Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD380000, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM2_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_RDCTRL @ 0XFD390000</p>
+
+ Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled
+ PSU_AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH 0x0
+
+ Read Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD390000, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM3_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_RDCTRL @ 0XFD3A0000</p>
+
+ Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled
+ PSU_AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH 0x0
+
+ Read Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD3A0000, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM4_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_RDCTRL @ 0XFD3B0000</p>
+
+ Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled
+ PSU_AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH 0x0
+
+ Read Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD3B0000, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM5_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_RDCTRL @ 0XFF9B0000</p>
+
+ Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled
+ PSU_AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH 0x0
+
+ Read Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFF9B0000, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM6_AFIFM_RDCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_WRCTRL @ 0XFD360014</p>
+
+ Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled
+ PSU_AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH 0x0
+
+ Write Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD360014, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM0_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_WRCTRL @ 0XFD370014</p>
+
+ Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled
+ PSU_AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH 0x0
+
+ Write Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD370014, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM1_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_WRCTRL @ 0XFD380014</p>
+
+ Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled
+ PSU_AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH 0x0
+
+ Write Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD380014, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM2_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_WRCTRL @ 0XFD390014</p>
+
+ Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled
+ PSU_AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH 0x0
+
+ Write Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD390014, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM3_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_WRCTRL @ 0XFD3A0014</p>
+
+ Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled
+ PSU_AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH 0x0
+
+ Write Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD3A0014, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM4_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_WRCTRL @ 0XFD3B0014</p>
+
+ Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled
+ PSU_AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH 0x0
+
+ Write Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFD3B0014, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM5_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
+ /*Register : AFIFM_WRCTRL @ 0XFF9B0014</p>
+
+ Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled
+ PSU_AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH 0x0
+
+ Write Channel Control Register
+ (OFFSET, MASK, VALUE) (0XFF9B0014, 0x00000003U ,0x00000000U)
+ RegMask = (AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_MASK | 0 );
+
+ RegVal = ((0x00000000U << AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+ | 0 ) & RegMask); */
+ PSU_Mask_Write (AFIFM6_AFIFM_WRCTRL_OFFSET ,0x00000003U ,0x00000000U);
+ /*############################################################################################################################ */
+
// : PS-PL POWER UP REQUEST
/*Register : REQ_PWRUP_INT_EN @ 0XFFD80118</p>
unsigned int regval = 0;
- ////////////////////////////////////////////////////////////////////////////////
- // RDBI work around code start
- ////////////////////////////////////////////////////////////////////////////////
- ////////////////////////////////////////////////////////////////////////////////
- // RDBI work around code end
- ////////////////////////////////////////////////////////////////////////////////
int dpll_divisor;
dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U;
- if (dpll_divisor != 0 && !dpll_divisor)
- dpll_divisor++;
prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U);
prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
Xil_Out32(0xFD080004U, 0x00040003U);
prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U);
prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U);
prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U);
+ prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor);
Xil_Out32(0xFD080004U, 0x40040071U);
while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U);
Xil_Out32(0xFD080004U, 0x40040001U);
Xil_Out32(0xFD070180U, 0x01000040U);
Xil_Out32(0xFD070060U, 0x00000000U);
prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
- ////////////////////////////////////////////////////////////////////////////////
- // RDBI work around code start
- ////////////////////////////////////////////////////////////////////////////////
- prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
- prog_reg (0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
- prog_reg (0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000001U);
- int DQ0RBD_0;
- DQ0RBD_0 = (Xil_In32(0xFD080750U) & 0x0000003FU) >> 0x00000000U;
- int DQ0RBD_1;
- DQ0RBD_1 = (Xil_In32(0xFD080750U) & 0x00003F00U) >> 0x00000008U;
- int DQ0RBD_2;
- DQ0RBD_2 = (Xil_In32(0xFD080750U) & 0x003F0000U) >> 0x00000010U;
- int DQ0RBD_3;
- DQ0RBD_3 = (Xil_In32(0xFD080750U) & 0x3F000000U) >> 0x00000018U;
- int DQ0RBD_4;
- DQ0RBD_4 = (Xil_In32(0xFD080754U) & 0x0000003FU) >> 0x00000000U;
- int DQ0RBD_5;
- DQ0RBD_5 = (Xil_In32(0xFD080754U) & 0x00003F00U) >> 0x00000008U;
- int DQ0RBD_6;
- DQ0RBD_6 = (Xil_In32(0xFD080754U) & 0x003F0000U) >> 0x00000010U;
- int DQ0RBD_7;
- DQ0RBD_7 = (Xil_In32(0xFD080754U) & 0x3F000000U) >> 0x00000018U;
- int DQ1RBD_0;
- DQ1RBD_0 = (Xil_In32(0xFD080850U) & 0x0000003FU) >> 0x00000000U;
- int DQ1RBD_1;
- DQ1RBD_1 = (Xil_In32(0xFD080850U) & 0x00003F00U) >> 0x00000008U;
- int DQ1RBD_2;
- DQ1RBD_2 = (Xil_In32(0xFD080850U) & 0x003F0000U) >> 0x00000010U;
- int DQ1RBD_3;
- DQ1RBD_3 = (Xil_In32(0xFD080850U) & 0x3F000000U) >> 0x00000018U;
- int DQ1RBD_4;
- DQ1RBD_4 = (Xil_In32(0xFD080854U) & 0x0000003FU) >> 0x00000000U;
- int DQ1RBD_5;
- DQ1RBD_5 = (Xil_In32(0xFD080854U) & 0x00003F00U) >> 0x00000008U;
- int DQ1RBD_6;
- DQ1RBD_6 = (Xil_In32(0xFD080854U) & 0x003F0000U) >> 0x00000010U;
- int DQ1RBD_7;
- DQ1RBD_7 = (Xil_In32(0xFD080854U) & 0x3F000000U) >> 0x00000018U;
- int DQ2RBD_0;
- DQ2RBD_0 = (Xil_In32(0xFD080950U) & 0x0000003FU) >> 0x00000000U;
- int DQ2RBD_1;
- DQ2RBD_1 = (Xil_In32(0xFD080950U) & 0x00003F00U) >> 0x00000008U;
- int DQ2RBD_2;
- DQ2RBD_2 = (Xil_In32(0xFD080950U) & 0x003F0000U) >> 0x00000010U;
- int DQ2RBD_3;
- DQ2RBD_3 = (Xil_In32(0xFD080950U) & 0x3F000000U) >> 0x00000018U;
- int DQ2RBD_4;
- DQ2RBD_4 = (Xil_In32(0xFD080954U) & 0x0000003FU) >> 0x00000000U;
- int DQ2RBD_5;
- DQ2RBD_5 = (Xil_In32(0xFD080954U) & 0x00003F00U) >> 0x00000008U;
- int DQ2RBD_6;
- DQ2RBD_6 = (Xil_In32(0xFD080954U) & 0x003F0000U) >> 0x00000010U;
- int DQ2RBD_7;
- DQ2RBD_7 = (Xil_In32(0xFD080954U) & 0x3F000000U) >> 0x00000018U;
- int DQ3RBD_0;
- DQ3RBD_0 = (Xil_In32(0xFD080A50U) & 0x0000003FU) >> 0x00000000U;
- int DQ3RBD_1;
- DQ3RBD_1 = (Xil_In32(0xFD080A50U) & 0x00003F00U) >> 0x00000008U;
- int DQ3RBD_2;
- DQ3RBD_2 = (Xil_In32(0xFD080A50U) & 0x003F0000U) >> 0x00000010U;
- int DQ3RBD_3;
- DQ3RBD_3 = (Xil_In32(0xFD080A50U) & 0x3F000000U) >> 0x00000018U;
- int DQ3RBD_4;
- DQ3RBD_4 = (Xil_In32(0xFD080A54U) & 0x0000003FU) >> 0x00000000U;
- int DQ3RBD_5;
- DQ3RBD_5 = (Xil_In32(0xFD080A54U) & 0x00003F00U) >> 0x00000008U;
- int DQ3RBD_6;
- DQ3RBD_6 = (Xil_In32(0xFD080A54U) & 0x003F0000U) >> 0x00000010U;
- int DQ3RBD_7;
- DQ3RBD_7 = (Xil_In32(0xFD080A54U) & 0x3F000000U) >> 0x00000018U;
- int DQ4RBD_0;
- DQ4RBD_0 = (Xil_In32(0xFD080B50U) & 0x0000003FU) >> 0x00000000U;
- int DQ4RBD_1;
- DQ4RBD_1 = (Xil_In32(0xFD080B50U) & 0x00003F00U) >> 0x00000008U;
- int DQ4RBD_2;
- DQ4RBD_2 = (Xil_In32(0xFD080B50U) & 0x003F0000U) >> 0x00000010U;
- int DQ4RBD_3;
- DQ4RBD_3 = (Xil_In32(0xFD080B50U) & 0x3F000000U) >> 0x00000018U;
- int DQ4RBD_4;
- DQ4RBD_4 = (Xil_In32(0xFD080B54U) & 0x0000003FU) >> 0x00000000U;
- int DQ4RBD_5;
- DQ4RBD_5 = (Xil_In32(0xFD080B54U) & 0x00003F00U) >> 0x00000008U;
- int DQ4RBD_6;
- DQ4RBD_6 = (Xil_In32(0xFD080B54U) & 0x003F0000U) >> 0x00000010U;
- int DQ4RBD_7;
- DQ4RBD_7 = (Xil_In32(0xFD080B54U) & 0x3F000000U) >> 0x00000018U;
- int DQ5RBD_0;
- DQ5RBD_0 = (Xil_In32(0xFD080C50U) & 0x0000003FU) >> 0x00000000U;
- int DQ5RBD_1;
- DQ5RBD_1 = (Xil_In32(0xFD080C50U) & 0x00003F00U) >> 0x00000008U;
- int DQ5RBD_2;
- DQ5RBD_2 = (Xil_In32(0xFD080C50U) & 0x003F0000U) >> 0x00000010U;
- int DQ5RBD_3;
- DQ5RBD_3 = (Xil_In32(0xFD080C50U) & 0x3F000000U) >> 0x00000018U;
- int DQ5RBD_4;
- DQ5RBD_4 = (Xil_In32(0xFD080C54U) & 0x0000003FU) >> 0x00000000U;
- int DQ5RBD_5;
- DQ5RBD_5 = (Xil_In32(0xFD080C54U) & 0x00003F00U) >> 0x00000008U;
- int DQ5RBD_6;
- DQ5RBD_6 = (Xil_In32(0xFD080C54U) & 0x003F0000U) >> 0x00000010U;
- int DQ5RBD_7;
- DQ5RBD_7 = (Xil_In32(0xFD080C54U) & 0x3F000000U) >> 0x00000018U;
- int DQ6RBD_0;
- DQ6RBD_0 = (Xil_In32(0xFD080D50U) & 0x0000003FU) >> 0x00000000U;
- int DQ6RBD_1;
- DQ6RBD_1 = (Xil_In32(0xFD080D50U) & 0x00003F00U) >> 0x00000008U;
- int DQ6RBD_2;
- DQ6RBD_2 = (Xil_In32(0xFD080D50U) & 0x003F0000U) >> 0x00000010U;
- int DQ6RBD_3;
- DQ6RBD_3 = (Xil_In32(0xFD080D50U) & 0x3F000000U) >> 0x00000018U;
- int DQ6RBD_4;
- DQ6RBD_4 = (Xil_In32(0xFD080D54U) & 0x0000003FU) >> 0x00000000U;
- int DQ6RBD_5;
- DQ6RBD_5 = (Xil_In32(0xFD080D54U) & 0x00003F00U) >> 0x00000008U;
- int DQ6RBD_6;
- DQ6RBD_6 = (Xil_In32(0xFD080D54U) & 0x003F0000U) >> 0x00000010U;
- int DQ6RBD_7;
- DQ6RBD_7 = (Xil_In32(0xFD080D54U) & 0x3F000000U) >> 0x00000018U;
- int DQ7RBD_0;
- DQ7RBD_0 = (Xil_In32(0xFD080E50U) & 0x0000003FU) >> 0x00000000U;
- int DQ7RBD_1;
- DQ7RBD_1 = (Xil_In32(0xFD080E50U) & 0x00003F00U) >> 0x00000008U;
- int DQ7RBD_2;
- DQ7RBD_2 = (Xil_In32(0xFD080E50U) & 0x003F0000U) >> 0x00000010U;
- int DQ7RBD_3;
- DQ7RBD_3 = (Xil_In32(0xFD080E50U) & 0x3F000000U) >> 0x00000018U;
- int DQ7RBD_4;
- DQ7RBD_4 = (Xil_In32(0xFD080E54U) & 0x0000003FU) >> 0x00000000U;
- int DQ7RBD_5;
- DQ7RBD_5 = (Xil_In32(0xFD080E54U) & 0x00003F00U) >> 0x00000008U;
- int DQ7RBD_6;
- DQ7RBD_6 = (Xil_In32(0xFD080E54U) & 0x003F0000U) >> 0x00000010U;
- int DQ7RBD_7;
- DQ7RBD_7 = (Xil_In32(0xFD080E54U) & 0x3F000000U) >> 0x00000018U;
-
-// ** declare variables used for calculation **
-
- int cal_byte0,cal_byte1,cal_byte2,cal_byte3,cal_byte4,cal_byte5,cal_byte6,cal_byte7; //,cal_byte8;
-
- cal_byte0 = ((DQ0RBD_0 + DQ0RBD_1 + DQ0RBD_2 + DQ0RBD_3 + DQ0RBD_4 + DQ0RBD_5 + DQ0RBD_6 + DQ0RBD_7)/8);
- cal_byte1 = ((DQ1RBD_0 + DQ1RBD_1 + DQ1RBD_2 + DQ1RBD_3 + DQ1RBD_4 + DQ1RBD_5 + DQ1RBD_6 + DQ1RBD_7)/8);
- cal_byte2 = ((DQ2RBD_0 + DQ2RBD_1 + DQ2RBD_2 + DQ2RBD_3 + DQ2RBD_4 + DQ2RBD_5 + DQ2RBD_6 + DQ2RBD_7)/8);
- cal_byte3 = ((DQ3RBD_0 + DQ3RBD_1 + DQ3RBD_2 + DQ3RBD_3 + DQ3RBD_4 + DQ3RBD_5 + DQ3RBD_6 + DQ3RBD_7)/8);
- cal_byte4 = ((DQ4RBD_0 + DQ4RBD_1 + DQ4RBD_2 + DQ4RBD_3 + DQ4RBD_4 + DQ4RBD_5 + DQ4RBD_6 + DQ4RBD_7)/8);
- cal_byte5 = ((DQ5RBD_0 + DQ5RBD_1 + DQ5RBD_2 + DQ5RBD_3 + DQ5RBD_4 + DQ5RBD_5 + DQ5RBD_6 + DQ5RBD_7)/8);
- cal_byte6 = ((DQ6RBD_0 + DQ6RBD_1 + DQ6RBD_2 + DQ6RBD_3 + DQ6RBD_4 + DQ6RBD_5 + DQ6RBD_6 + DQ6RBD_7)/8);
- cal_byte7 = ((DQ7RBD_0 + DQ7RBD_1 + DQ7RBD_2 + DQ7RBD_3 + DQ7RBD_4 + DQ7RBD_5 + DQ7RBD_6 + DQ7RBD_7)/8);
- prog_reg (0xFD080758U, 0x0000003FU, 0, cal_byte0);
- prog_reg (0xFD080858U, 0x0000003FU, 0, cal_byte1);
- prog_reg (0xFD080958U, 0x0000003FU, 0, cal_byte2);
- prog_reg (0xFD080A58U, 0x0000003FU, 0, cal_byte3);
- prog_reg (0xFD080B58U, 0x0000003FU, 0, cal_byte4);
- prog_reg (0xFD080C58U, 0x0000003FU, 0, cal_byte5);
- prog_reg (0xFD080D58U, 0x0000003FU, 0, cal_byte6);
- prog_reg (0xFD080E58U, 0x0000003FU, 0, cal_byte7);
- prog_reg (0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
- prog_reg (0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
- prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
- ////////////////////////////////////////////////////////////////////////////////
- // RDBI work around code end
- ////////////////////////////////////////////////////////////////////////////////
return 1;
}
int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
int i = 0;
while ((*addr & mask)!= value) {
if (i == PSU_MASK_POLL_TIME) {
}
int mask_poll(u32 add , u32 mask) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
int i = 0;
while (!(*addr & mask)) {
if (i == PSU_MASK_POLL_TIME) {
}
u32 mask_read(u32 add , u32 mask ) {
- volatile u32 *addr = (volatile u32*) add;
+ volatile u32 *addr = (volatile u32*)(unsigned long) add;
u32 val = (*addr & mask);
//xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
return val;
Xil_Out32(0xFD690030, tmp_regval);
}
+int psu_init_xppu_aper_ram() {
+ unsigned long APER_OFFSET = 0xFF981000;
+ int i = 0;
+ for (; i <= 400; i++) {
+ PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U);
+ APER_OFFSET = APER_OFFSET + 0x4;
+ }
+
+ return 0;
+}
+
int psu_lpd_protection() {
+ psu_init_xppu_aper_ram();
psu_lpd_xppu_data();
- return 1;
+ return 0;
}
int psu_ddr_protection() {
psu_ddr_xmpu3_data();
psu_ddr_xmpu4_data();
psu_ddr_xmpu5_data();
- return 1;
+ return 0;
}
int psu_ocm_protection() {
psu_ocm_xmpu_data();
- return 1;
+ return 0;
}
int psu_fpd_protection() {
psu_fpd_xmpu_data();
- return 1;
+ return 0;
+}
+
+int psu_protection_lock() {
+ psu_protection_lock_data();
+ return 0;
}
int psu_protection() {
- psu_lpd_protection();
psu_ddr_protection();
psu_ocm_protection();
psu_fpd_protection();
- return 1;
+ psu_lpd_protection();
+ return 0;
}
#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 0XFF5E0128
#undef CRF_APB_SATA_REF_CTRL_OFFSET
#define CRF_APB_SATA_REF_CTRL_OFFSET 0XFD1A00A0
-#undef CRF_APB_PCIE_REF_CTRL_OFFSET
-#define CRF_APB_PCIE_REF_CTRL_OFFSET 0XFD1A00B4
#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET
#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 0XFD1A0070
#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-/*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
- es of the new clock. This is not usually an issue, but designers must be aware.)*/
-#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL
-#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
-#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK
-#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500
-#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0
-#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U
-
-/*Clock active signal. Switch to 0 to disable the clock*/
-#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL
-#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
-#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK
-#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500
-#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24
-#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U
-
-/*6 bit divider*/
-#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL
-#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
-#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK
-#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500
-#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8
-#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U
-
/*6 bit divider*/
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U
/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
#undef CRL_APB_RST_LPD_IOU2_OFFSET
#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238
+#undef TPIU_LAR_OFFSET
+#define TPIU_LAR_OFFSET 0XFE980FB0
+#undef TPIU_CURRENT_PORT_SIZE_OFFSET
+#define TPIU_CURRENT_PORT_SIZE_OFFSET 0XFE980004
+#undef TPIU_LAR_OFFSET
+#define TPIU_LAR_OFFSET 0XFE980FB0
#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET
#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 0XFF000034
#undef UART0_BAUD_RATE_GEN_REG0_OFFSET
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
-/*PCIE config reset*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
-
-/*PCIE control block level reset*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
-
-/*PCIE bridge block level reset (AXI interface)*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
-
/*Display Port block level reset (includes DPDMA)*/
#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2
#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U
+/*A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the a
+ fect of removing write access.*/
+#undef TPIU_LAR_ACCESS_W_DEFVAL
+#undef TPIU_LAR_ACCESS_W_SHIFT
+#undef TPIU_LAR_ACCESS_W_MASK
+#define TPIU_LAR_ACCESS_W_DEFVAL
+#define TPIU_LAR_ACCESS_W_SHIFT 0
+#define TPIU_LAR_ACCESS_W_MASK 0xFFFFFFFFU
+
+/*Indicates whether the current port size of the TPIU is 32 bits.*/
+#undef TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_DEFVAL
+#undef TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_SHIFT
+#undef TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_MASK
+#define TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_DEFVAL 0x00000001
+#define TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_SHIFT 31
+#define TPIU_CURRENT_PORT_SIZE_PORT_SIZE_32_MASK 0x80000000U
+
+/*A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the a
+ fect of removing write access.*/
+#undef TPIU_LAR_ACCESS_W_DEFVAL
+#undef TPIU_LAR_ACCESS_W_SHIFT
+#undef TPIU_LAR_ACCESS_W_MASK
+#define TPIU_LAR_ACCESS_W_DEFVAL
+#define TPIU_LAR_ACCESS_W_SHIFT 0
+#define TPIU_LAR_ACCESS_W_MASK 0xFFFFFFFFU
+
/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
#define LPD_XPPU_CFG_MASTER_ID07_OFFSET 0XFF98011C
#undef LPD_XPPU_CFG_MASTER_ID19_OFFSET
#define LPD_XPPU_CFG_MASTER_ID19_OFFSET 0XFF98014C
-#undef LPD_XPPU_CFG_APERPERM_000_OFFSET
-#define LPD_XPPU_CFG_APERPERM_000_OFFSET 0XFF981000
-#undef LPD_XPPU_CFG_APERPERM_001_OFFSET
-#define LPD_XPPU_CFG_APERPERM_001_OFFSET 0XFF981004
-#undef LPD_XPPU_CFG_APERPERM_002_OFFSET
-#define LPD_XPPU_CFG_APERPERM_002_OFFSET 0XFF981008
-#undef LPD_XPPU_CFG_APERPERM_003_OFFSET
-#define LPD_XPPU_CFG_APERPERM_003_OFFSET 0XFF98100C
-#undef LPD_XPPU_CFG_APERPERM_004_OFFSET
-#define LPD_XPPU_CFG_APERPERM_004_OFFSET 0XFF981010
-#undef LPD_XPPU_CFG_APERPERM_005_OFFSET
-#define LPD_XPPU_CFG_APERPERM_005_OFFSET 0XFF981014
-#undef LPD_XPPU_CFG_APERPERM_006_OFFSET
-#define LPD_XPPU_CFG_APERPERM_006_OFFSET 0XFF981018
-#undef LPD_XPPU_CFG_APERPERM_007_OFFSET
-#define LPD_XPPU_CFG_APERPERM_007_OFFSET 0XFF98101C
-#undef LPD_XPPU_CFG_APERPERM_008_OFFSET
-#define LPD_XPPU_CFG_APERPERM_008_OFFSET 0XFF981020
-#undef LPD_XPPU_CFG_APERPERM_009_OFFSET
-#define LPD_XPPU_CFG_APERPERM_009_OFFSET 0XFF981024
-#undef LPD_XPPU_CFG_APERPERM_010_OFFSET
-#define LPD_XPPU_CFG_APERPERM_010_OFFSET 0XFF981028
-#undef LPD_XPPU_CFG_APERPERM_011_OFFSET
-#define LPD_XPPU_CFG_APERPERM_011_OFFSET 0XFF98102C
-#undef LPD_XPPU_CFG_APERPERM_012_OFFSET
-#define LPD_XPPU_CFG_APERPERM_012_OFFSET 0XFF981030
-#undef LPD_XPPU_CFG_APERPERM_013_OFFSET
-#define LPD_XPPU_CFG_APERPERM_013_OFFSET 0XFF981034
-#undef LPD_XPPU_CFG_APERPERM_014_OFFSET
-#define LPD_XPPU_CFG_APERPERM_014_OFFSET 0XFF981038
-#undef LPD_XPPU_CFG_APERPERM_015_OFFSET
-#define LPD_XPPU_CFG_APERPERM_015_OFFSET 0XFF98103C
-#undef LPD_XPPU_CFG_APERPERM_016_OFFSET
-#define LPD_XPPU_CFG_APERPERM_016_OFFSET 0XFF981040
-#undef LPD_XPPU_CFG_APERPERM_017_OFFSET
-#define LPD_XPPU_CFG_APERPERM_017_OFFSET 0XFF981044
-#undef LPD_XPPU_CFG_APERPERM_018_OFFSET
-#define LPD_XPPU_CFG_APERPERM_018_OFFSET 0XFF981048
-#undef LPD_XPPU_CFG_APERPERM_019_OFFSET
-#define LPD_XPPU_CFG_APERPERM_019_OFFSET 0XFF98104C
-#undef LPD_XPPU_CFG_APERPERM_020_OFFSET
-#define LPD_XPPU_CFG_APERPERM_020_OFFSET 0XFF981050
-#undef LPD_XPPU_CFG_APERPERM_021_OFFSET
-#define LPD_XPPU_CFG_APERPERM_021_OFFSET 0XFF981054
-#undef LPD_XPPU_CFG_APERPERM_022_OFFSET
-#define LPD_XPPU_CFG_APERPERM_022_OFFSET 0XFF981058
-#undef LPD_XPPU_CFG_APERPERM_023_OFFSET
-#define LPD_XPPU_CFG_APERPERM_023_OFFSET 0XFF98105C
-#undef LPD_XPPU_CFG_APERPERM_024_OFFSET
-#define LPD_XPPU_CFG_APERPERM_024_OFFSET 0XFF981060
-#undef LPD_XPPU_CFG_APERPERM_025_OFFSET
-#define LPD_XPPU_CFG_APERPERM_025_OFFSET 0XFF981064
-#undef LPD_XPPU_CFG_APERPERM_026_OFFSET
-#define LPD_XPPU_CFG_APERPERM_026_OFFSET 0XFF981068
-#undef LPD_XPPU_CFG_APERPERM_027_OFFSET
-#define LPD_XPPU_CFG_APERPERM_027_OFFSET 0XFF98106C
-#undef LPD_XPPU_CFG_APERPERM_028_OFFSET
-#define LPD_XPPU_CFG_APERPERM_028_OFFSET 0XFF981070
-#undef LPD_XPPU_CFG_APERPERM_029_OFFSET
-#define LPD_XPPU_CFG_APERPERM_029_OFFSET 0XFF981074
-#undef LPD_XPPU_CFG_APERPERM_030_OFFSET
-#define LPD_XPPU_CFG_APERPERM_030_OFFSET 0XFF981078
-#undef LPD_XPPU_CFG_APERPERM_031_OFFSET
-#define LPD_XPPU_CFG_APERPERM_031_OFFSET 0XFF98107C
-#undef LPD_XPPU_CFG_APERPERM_032_OFFSET
-#define LPD_XPPU_CFG_APERPERM_032_OFFSET 0XFF981080
-#undef LPD_XPPU_CFG_APERPERM_033_OFFSET
-#define LPD_XPPU_CFG_APERPERM_033_OFFSET 0XFF981084
-#undef LPD_XPPU_CFG_APERPERM_034_OFFSET
-#define LPD_XPPU_CFG_APERPERM_034_OFFSET 0XFF981088
-#undef LPD_XPPU_CFG_APERPERM_035_OFFSET
-#define LPD_XPPU_CFG_APERPERM_035_OFFSET 0XFF98108C
-#undef LPD_XPPU_CFG_APERPERM_036_OFFSET
-#define LPD_XPPU_CFG_APERPERM_036_OFFSET 0XFF981090
-#undef LPD_XPPU_CFG_APERPERM_037_OFFSET
-#define LPD_XPPU_CFG_APERPERM_037_OFFSET 0XFF981094
-#undef LPD_XPPU_CFG_APERPERM_038_OFFSET
-#define LPD_XPPU_CFG_APERPERM_038_OFFSET 0XFF981098
-#undef LPD_XPPU_CFG_APERPERM_039_OFFSET
-#define LPD_XPPU_CFG_APERPERM_039_OFFSET 0XFF98109C
-#undef LPD_XPPU_CFG_APERPERM_040_OFFSET
-#define LPD_XPPU_CFG_APERPERM_040_OFFSET 0XFF9810A0
-#undef LPD_XPPU_CFG_APERPERM_041_OFFSET
-#define LPD_XPPU_CFG_APERPERM_041_OFFSET 0XFF9810A4
-#undef LPD_XPPU_CFG_APERPERM_042_OFFSET
-#define LPD_XPPU_CFG_APERPERM_042_OFFSET 0XFF9810A8
-#undef LPD_XPPU_CFG_APERPERM_043_OFFSET
-#define LPD_XPPU_CFG_APERPERM_043_OFFSET 0XFF9810AC
-#undef LPD_XPPU_CFG_APERPERM_044_OFFSET
-#define LPD_XPPU_CFG_APERPERM_044_OFFSET 0XFF9810B0
-#undef LPD_XPPU_CFG_APERPERM_045_OFFSET
-#define LPD_XPPU_CFG_APERPERM_045_OFFSET 0XFF9810B4
-#undef LPD_XPPU_CFG_APERPERM_046_OFFSET
-#define LPD_XPPU_CFG_APERPERM_046_OFFSET 0XFF9810B8
-#undef LPD_XPPU_CFG_APERPERM_047_OFFSET
-#define LPD_XPPU_CFG_APERPERM_047_OFFSET 0XFF9810BC
#undef LPD_XPPU_CFG_APERPERM_048_OFFSET
#define LPD_XPPU_CFG_APERPERM_048_OFFSET 0XFF9810C0
#undef LPD_XPPU_CFG_APERPERM_049_OFFSET
#define LPD_XPPU_CFG_APERPERM_050_OFFSET 0XFF9810C8
#undef LPD_XPPU_CFG_APERPERM_051_OFFSET
#define LPD_XPPU_CFG_APERPERM_051_OFFSET 0XFF9810CC
-#undef LPD_XPPU_CFG_APERPERM_052_OFFSET
-#define LPD_XPPU_CFG_APERPERM_052_OFFSET 0XFF9810D0
-#undef LPD_XPPU_CFG_APERPERM_053_OFFSET
-#define LPD_XPPU_CFG_APERPERM_053_OFFSET 0XFF9810D4
-#undef LPD_XPPU_CFG_APERPERM_054_OFFSET
-#define LPD_XPPU_CFG_APERPERM_054_OFFSET 0XFF9810D8
-#undef LPD_XPPU_CFG_APERPERM_055_OFFSET
-#define LPD_XPPU_CFG_APERPERM_055_OFFSET 0XFF9810DC
-#undef LPD_XPPU_CFG_APERPERM_056_OFFSET
-#define LPD_XPPU_CFG_APERPERM_056_OFFSET 0XFF9810E0
-#undef LPD_XPPU_CFG_APERPERM_057_OFFSET
-#define LPD_XPPU_CFG_APERPERM_057_OFFSET 0XFF9810E4
-#undef LPD_XPPU_CFG_APERPERM_058_OFFSET
-#define LPD_XPPU_CFG_APERPERM_058_OFFSET 0XFF9810E8
-#undef LPD_XPPU_CFG_APERPERM_059_OFFSET
-#define LPD_XPPU_CFG_APERPERM_059_OFFSET 0XFF9810EC
-#undef LPD_XPPU_CFG_APERPERM_060_OFFSET
-#define LPD_XPPU_CFG_APERPERM_060_OFFSET 0XFF9810F0
-#undef LPD_XPPU_CFG_APERPERM_061_OFFSET
-#define LPD_XPPU_CFG_APERPERM_061_OFFSET 0XFF9810F4
-#undef LPD_XPPU_CFG_APERPERM_062_OFFSET
-#define LPD_XPPU_CFG_APERPERM_062_OFFSET 0XFF9810F8
-#undef LPD_XPPU_CFG_APERPERM_063_OFFSET
-#define LPD_XPPU_CFG_APERPERM_063_OFFSET 0XFF9810FC
-#undef LPD_XPPU_CFG_APERPERM_064_OFFSET
-#define LPD_XPPU_CFG_APERPERM_064_OFFSET 0XFF981100
-#undef LPD_XPPU_CFG_APERPERM_065_OFFSET
-#define LPD_XPPU_CFG_APERPERM_065_OFFSET 0XFF981104
-#undef LPD_XPPU_CFG_APERPERM_066_OFFSET
-#define LPD_XPPU_CFG_APERPERM_066_OFFSET 0XFF981108
-#undef LPD_XPPU_CFG_APERPERM_067_OFFSET
-#define LPD_XPPU_CFG_APERPERM_067_OFFSET 0XFF98110C
-#undef LPD_XPPU_CFG_APERPERM_068_OFFSET
-#define LPD_XPPU_CFG_APERPERM_068_OFFSET 0XFF981110
-#undef LPD_XPPU_CFG_APERPERM_069_OFFSET
-#define LPD_XPPU_CFG_APERPERM_069_OFFSET 0XFF981114
-#undef LPD_XPPU_CFG_APERPERM_070_OFFSET
-#define LPD_XPPU_CFG_APERPERM_070_OFFSET 0XFF981118
-#undef LPD_XPPU_CFG_APERPERM_071_OFFSET
-#define LPD_XPPU_CFG_APERPERM_071_OFFSET 0XFF98111C
-#undef LPD_XPPU_CFG_APERPERM_072_OFFSET
-#define LPD_XPPU_CFG_APERPERM_072_OFFSET 0XFF981120
-#undef LPD_XPPU_CFG_APERPERM_073_OFFSET
-#define LPD_XPPU_CFG_APERPERM_073_OFFSET 0XFF981124
-#undef LPD_XPPU_CFG_APERPERM_074_OFFSET
-#define LPD_XPPU_CFG_APERPERM_074_OFFSET 0XFF981128
-#undef LPD_XPPU_CFG_APERPERM_075_OFFSET
-#define LPD_XPPU_CFG_APERPERM_075_OFFSET 0XFF98112C
-#undef LPD_XPPU_CFG_APERPERM_076_OFFSET
-#define LPD_XPPU_CFG_APERPERM_076_OFFSET 0XFF981130
-#undef LPD_XPPU_CFG_APERPERM_077_OFFSET
-#define LPD_XPPU_CFG_APERPERM_077_OFFSET 0XFF981134
-#undef LPD_XPPU_CFG_APERPERM_078_OFFSET
-#define LPD_XPPU_CFG_APERPERM_078_OFFSET 0XFF981138
-#undef LPD_XPPU_CFG_APERPERM_079_OFFSET
-#define LPD_XPPU_CFG_APERPERM_079_OFFSET 0XFF98113C
-#undef LPD_XPPU_CFG_APERPERM_080_OFFSET
-#define LPD_XPPU_CFG_APERPERM_080_OFFSET 0XFF981140
-#undef LPD_XPPU_CFG_APERPERM_081_OFFSET
-#define LPD_XPPU_CFG_APERPERM_081_OFFSET 0XFF981144
-#undef LPD_XPPU_CFG_APERPERM_082_OFFSET
-#define LPD_XPPU_CFG_APERPERM_082_OFFSET 0XFF981148
-#undef LPD_XPPU_CFG_APERPERM_083_OFFSET
-#define LPD_XPPU_CFG_APERPERM_083_OFFSET 0XFF98114C
-#undef LPD_XPPU_CFG_APERPERM_084_OFFSET
-#define LPD_XPPU_CFG_APERPERM_084_OFFSET 0XFF981150
-#undef LPD_XPPU_CFG_APERPERM_085_OFFSET
-#define LPD_XPPU_CFG_APERPERM_085_OFFSET 0XFF981154
-#undef LPD_XPPU_CFG_APERPERM_086_OFFSET
-#define LPD_XPPU_CFG_APERPERM_086_OFFSET 0XFF981158
-#undef LPD_XPPU_CFG_APERPERM_087_OFFSET
-#define LPD_XPPU_CFG_APERPERM_087_OFFSET 0XFF98115C
-#undef LPD_XPPU_CFG_APERPERM_088_OFFSET
-#define LPD_XPPU_CFG_APERPERM_088_OFFSET 0XFF981160
-#undef LPD_XPPU_CFG_APERPERM_089_OFFSET
-#define LPD_XPPU_CFG_APERPERM_089_OFFSET 0XFF981164
-#undef LPD_XPPU_CFG_APERPERM_090_OFFSET
-#define LPD_XPPU_CFG_APERPERM_090_OFFSET 0XFF981168
-#undef LPD_XPPU_CFG_APERPERM_091_OFFSET
-#define LPD_XPPU_CFG_APERPERM_091_OFFSET 0XFF98116C
-#undef LPD_XPPU_CFG_APERPERM_092_OFFSET
-#define LPD_XPPU_CFG_APERPERM_092_OFFSET 0XFF981170
-#undef LPD_XPPU_CFG_APERPERM_093_OFFSET
-#define LPD_XPPU_CFG_APERPERM_093_OFFSET 0XFF981174
-#undef LPD_XPPU_CFG_APERPERM_094_OFFSET
-#define LPD_XPPU_CFG_APERPERM_094_OFFSET 0XFF981178
-#undef LPD_XPPU_CFG_APERPERM_095_OFFSET
-#define LPD_XPPU_CFG_APERPERM_095_OFFSET 0XFF98117C
-#undef LPD_XPPU_CFG_APERPERM_096_OFFSET
-#define LPD_XPPU_CFG_APERPERM_096_OFFSET 0XFF981180
-#undef LPD_XPPU_CFG_APERPERM_097_OFFSET
-#define LPD_XPPU_CFG_APERPERM_097_OFFSET 0XFF981184
-#undef LPD_XPPU_CFG_APERPERM_098_OFFSET
-#define LPD_XPPU_CFG_APERPERM_098_OFFSET 0XFF981188
-#undef LPD_XPPU_CFG_APERPERM_099_OFFSET
-#define LPD_XPPU_CFG_APERPERM_099_OFFSET 0XFF98118C
-#undef LPD_XPPU_CFG_APERPERM_100_OFFSET
-#define LPD_XPPU_CFG_APERPERM_100_OFFSET 0XFF981190
-#undef LPD_XPPU_CFG_APERPERM_101_OFFSET
-#define LPD_XPPU_CFG_APERPERM_101_OFFSET 0XFF981194
-#undef LPD_XPPU_CFG_APERPERM_102_OFFSET
-#define LPD_XPPU_CFG_APERPERM_102_OFFSET 0XFF981198
-#undef LPD_XPPU_CFG_APERPERM_103_OFFSET
-#define LPD_XPPU_CFG_APERPERM_103_OFFSET 0XFF98119C
-#undef LPD_XPPU_CFG_APERPERM_104_OFFSET
-#define LPD_XPPU_CFG_APERPERM_104_OFFSET 0XFF9811A0
-#undef LPD_XPPU_CFG_APERPERM_105_OFFSET
-#define LPD_XPPU_CFG_APERPERM_105_OFFSET 0XFF9811A4
-#undef LPD_XPPU_CFG_APERPERM_106_OFFSET
-#define LPD_XPPU_CFG_APERPERM_106_OFFSET 0XFF9811A8
-#undef LPD_XPPU_CFG_APERPERM_107_OFFSET
-#define LPD_XPPU_CFG_APERPERM_107_OFFSET 0XFF9811AC
-#undef LPD_XPPU_CFG_APERPERM_108_OFFSET
-#define LPD_XPPU_CFG_APERPERM_108_OFFSET 0XFF9811B0
-#undef LPD_XPPU_CFG_APERPERM_109_OFFSET
-#define LPD_XPPU_CFG_APERPERM_109_OFFSET 0XFF9811B4
-#undef LPD_XPPU_CFG_APERPERM_110_OFFSET
-#define LPD_XPPU_CFG_APERPERM_110_OFFSET 0XFF9811B8
-#undef LPD_XPPU_CFG_APERPERM_111_OFFSET
-#define LPD_XPPU_CFG_APERPERM_111_OFFSET 0XFF9811BC
-#undef LPD_XPPU_CFG_APERPERM_112_OFFSET
-#define LPD_XPPU_CFG_APERPERM_112_OFFSET 0XFF9811C0
-#undef LPD_XPPU_CFG_APERPERM_113_OFFSET
-#define LPD_XPPU_CFG_APERPERM_113_OFFSET 0XFF9811C4
-#undef LPD_XPPU_CFG_APERPERM_114_OFFSET
-#define LPD_XPPU_CFG_APERPERM_114_OFFSET 0XFF9811C8
-#undef LPD_XPPU_CFG_APERPERM_115_OFFSET
-#define LPD_XPPU_CFG_APERPERM_115_OFFSET 0XFF9811CC
-#undef LPD_XPPU_CFG_APERPERM_116_OFFSET
-#define LPD_XPPU_CFG_APERPERM_116_OFFSET 0XFF9811D0
-#undef LPD_XPPU_CFG_APERPERM_117_OFFSET
-#define LPD_XPPU_CFG_APERPERM_117_OFFSET 0XFF9811D4
-#undef LPD_XPPU_CFG_APERPERM_118_OFFSET
-#define LPD_XPPU_CFG_APERPERM_118_OFFSET 0XFF9811D8
-#undef LPD_XPPU_CFG_APERPERM_119_OFFSET
-#define LPD_XPPU_CFG_APERPERM_119_OFFSET 0XFF9811DC
-#undef LPD_XPPU_CFG_APERPERM_120_OFFSET
-#define LPD_XPPU_CFG_APERPERM_120_OFFSET 0XFF9811E0
-#undef LPD_XPPU_CFG_APERPERM_121_OFFSET
-#define LPD_XPPU_CFG_APERPERM_121_OFFSET 0XFF9811E4
-#undef LPD_XPPU_CFG_APERPERM_122_OFFSET
-#define LPD_XPPU_CFG_APERPERM_122_OFFSET 0XFF9811E8
-#undef LPD_XPPU_CFG_APERPERM_123_OFFSET
-#define LPD_XPPU_CFG_APERPERM_123_OFFSET 0XFF9811EC
-#undef LPD_XPPU_CFG_APERPERM_124_OFFSET
-#define LPD_XPPU_CFG_APERPERM_124_OFFSET 0XFF9811F0
-#undef LPD_XPPU_CFG_APERPERM_125_OFFSET
-#define LPD_XPPU_CFG_APERPERM_125_OFFSET 0XFF9811F4
-#undef LPD_XPPU_CFG_APERPERM_126_OFFSET
-#define LPD_XPPU_CFG_APERPERM_126_OFFSET 0XFF9811F8
-#undef LPD_XPPU_CFG_APERPERM_127_OFFSET
-#define LPD_XPPU_CFG_APERPERM_127_OFFSET 0XFF9811FC
-#undef LPD_XPPU_CFG_APERPERM_128_OFFSET
-#define LPD_XPPU_CFG_APERPERM_128_OFFSET 0XFF981200
-#undef LPD_XPPU_CFG_APERPERM_129_OFFSET
-#define LPD_XPPU_CFG_APERPERM_129_OFFSET 0XFF981204
-#undef LPD_XPPU_CFG_APERPERM_130_OFFSET
-#define LPD_XPPU_CFG_APERPERM_130_OFFSET 0XFF981208
-#undef LPD_XPPU_CFG_APERPERM_131_OFFSET
-#define LPD_XPPU_CFG_APERPERM_131_OFFSET 0XFF98120C
-#undef LPD_XPPU_CFG_APERPERM_132_OFFSET
-#define LPD_XPPU_CFG_APERPERM_132_OFFSET 0XFF981210
-#undef LPD_XPPU_CFG_APERPERM_133_OFFSET
-#define LPD_XPPU_CFG_APERPERM_133_OFFSET 0XFF981214
-#undef LPD_XPPU_CFG_APERPERM_134_OFFSET
-#define LPD_XPPU_CFG_APERPERM_134_OFFSET 0XFF981218
-#undef LPD_XPPU_CFG_APERPERM_135_OFFSET
-#define LPD_XPPU_CFG_APERPERM_135_OFFSET 0XFF98121C
-#undef LPD_XPPU_CFG_APERPERM_136_OFFSET
-#define LPD_XPPU_CFG_APERPERM_136_OFFSET 0XFF981220
-#undef LPD_XPPU_CFG_APERPERM_137_OFFSET
-#define LPD_XPPU_CFG_APERPERM_137_OFFSET 0XFF981224
-#undef LPD_XPPU_CFG_APERPERM_138_OFFSET
-#define LPD_XPPU_CFG_APERPERM_138_OFFSET 0XFF981228
-#undef LPD_XPPU_CFG_APERPERM_139_OFFSET
-#define LPD_XPPU_CFG_APERPERM_139_OFFSET 0XFF98122C
-#undef LPD_XPPU_CFG_APERPERM_140_OFFSET
-#define LPD_XPPU_CFG_APERPERM_140_OFFSET 0XFF981230
-#undef LPD_XPPU_CFG_APERPERM_141_OFFSET
-#define LPD_XPPU_CFG_APERPERM_141_OFFSET 0XFF981234
-#undef LPD_XPPU_CFG_APERPERM_142_OFFSET
-#define LPD_XPPU_CFG_APERPERM_142_OFFSET 0XFF981238
-#undef LPD_XPPU_CFG_APERPERM_143_OFFSET
-#define LPD_XPPU_CFG_APERPERM_143_OFFSET 0XFF98123C
-#undef LPD_XPPU_CFG_APERPERM_144_OFFSET
-#define LPD_XPPU_CFG_APERPERM_144_OFFSET 0XFF981240
-#undef LPD_XPPU_CFG_APERPERM_145_OFFSET
-#define LPD_XPPU_CFG_APERPERM_145_OFFSET 0XFF981244
-#undef LPD_XPPU_CFG_APERPERM_146_OFFSET
-#define LPD_XPPU_CFG_APERPERM_146_OFFSET 0XFF981248
-#undef LPD_XPPU_CFG_APERPERM_147_OFFSET
-#define LPD_XPPU_CFG_APERPERM_147_OFFSET 0XFF98124C
-#undef LPD_XPPU_CFG_APERPERM_148_OFFSET
-#define LPD_XPPU_CFG_APERPERM_148_OFFSET 0XFF981250
-#undef LPD_XPPU_CFG_APERPERM_149_OFFSET
-#define LPD_XPPU_CFG_APERPERM_149_OFFSET 0XFF981254
-#undef LPD_XPPU_CFG_APERPERM_150_OFFSET
-#define LPD_XPPU_CFG_APERPERM_150_OFFSET 0XFF981258
-#undef LPD_XPPU_CFG_APERPERM_151_OFFSET
-#define LPD_XPPU_CFG_APERPERM_151_OFFSET 0XFF98125C
-#undef LPD_XPPU_CFG_APERPERM_152_OFFSET
-#define LPD_XPPU_CFG_APERPERM_152_OFFSET 0XFF981260
-#undef LPD_XPPU_CFG_APERPERM_153_OFFSET
-#define LPD_XPPU_CFG_APERPERM_153_OFFSET 0XFF981264
-#undef LPD_XPPU_CFG_APERPERM_154_OFFSET
-#define LPD_XPPU_CFG_APERPERM_154_OFFSET 0XFF981268
-#undef LPD_XPPU_CFG_APERPERM_155_OFFSET
-#define LPD_XPPU_CFG_APERPERM_155_OFFSET 0XFF98126C
-#undef LPD_XPPU_CFG_APERPERM_156_OFFSET
-#define LPD_XPPU_CFG_APERPERM_156_OFFSET 0XFF981270
-#undef LPD_XPPU_CFG_APERPERM_157_OFFSET
-#define LPD_XPPU_CFG_APERPERM_157_OFFSET 0XFF981274
-#undef LPD_XPPU_CFG_APERPERM_158_OFFSET
-#define LPD_XPPU_CFG_APERPERM_158_OFFSET 0XFF981278
-#undef LPD_XPPU_CFG_APERPERM_159_OFFSET
-#define LPD_XPPU_CFG_APERPERM_159_OFFSET 0XFF98127C
-#undef LPD_XPPU_CFG_APERPERM_160_OFFSET
-#define LPD_XPPU_CFG_APERPERM_160_OFFSET 0XFF981280
-#undef LPD_XPPU_CFG_APERPERM_161_OFFSET
-#define LPD_XPPU_CFG_APERPERM_161_OFFSET 0XFF981284
-#undef LPD_XPPU_CFG_APERPERM_162_OFFSET
-#define LPD_XPPU_CFG_APERPERM_162_OFFSET 0XFF981288
-#undef LPD_XPPU_CFG_APERPERM_163_OFFSET
-#define LPD_XPPU_CFG_APERPERM_163_OFFSET 0XFF98128C
-#undef LPD_XPPU_CFG_APERPERM_164_OFFSET
-#define LPD_XPPU_CFG_APERPERM_164_OFFSET 0XFF981290
-#undef LPD_XPPU_CFG_APERPERM_165_OFFSET
-#define LPD_XPPU_CFG_APERPERM_165_OFFSET 0XFF981294
-#undef LPD_XPPU_CFG_APERPERM_166_OFFSET
-#define LPD_XPPU_CFG_APERPERM_166_OFFSET 0XFF981298
-#undef LPD_XPPU_CFG_APERPERM_167_OFFSET
-#define LPD_XPPU_CFG_APERPERM_167_OFFSET 0XFF98129C
-#undef LPD_XPPU_CFG_APERPERM_168_OFFSET
-#define LPD_XPPU_CFG_APERPERM_168_OFFSET 0XFF9812A0
-#undef LPD_XPPU_CFG_APERPERM_169_OFFSET
-#define LPD_XPPU_CFG_APERPERM_169_OFFSET 0XFF9812A4
-#undef LPD_XPPU_CFG_APERPERM_170_OFFSET
-#define LPD_XPPU_CFG_APERPERM_170_OFFSET 0XFF9812A8
-#undef LPD_XPPU_CFG_APERPERM_171_OFFSET
-#define LPD_XPPU_CFG_APERPERM_171_OFFSET 0XFF9812AC
-#undef LPD_XPPU_CFG_APERPERM_172_OFFSET
-#define LPD_XPPU_CFG_APERPERM_172_OFFSET 0XFF9812B0
-#undef LPD_XPPU_CFG_APERPERM_173_OFFSET
-#define LPD_XPPU_CFG_APERPERM_173_OFFSET 0XFF9812B4
-#undef LPD_XPPU_CFG_APERPERM_174_OFFSET
-#define LPD_XPPU_CFG_APERPERM_174_OFFSET 0XFF9812B8
-#undef LPD_XPPU_CFG_APERPERM_175_OFFSET
-#define LPD_XPPU_CFG_APERPERM_175_OFFSET 0XFF9812BC
-#undef LPD_XPPU_CFG_APERPERM_176_OFFSET
-#define LPD_XPPU_CFG_APERPERM_176_OFFSET 0XFF9812C0
-#undef LPD_XPPU_CFG_APERPERM_177_OFFSET
-#define LPD_XPPU_CFG_APERPERM_177_OFFSET 0XFF9812C4
-#undef LPD_XPPU_CFG_APERPERM_178_OFFSET
-#define LPD_XPPU_CFG_APERPERM_178_OFFSET 0XFF9812C8
-#undef LPD_XPPU_CFG_APERPERM_179_OFFSET
-#define LPD_XPPU_CFG_APERPERM_179_OFFSET 0XFF9812CC
-#undef LPD_XPPU_CFG_APERPERM_180_OFFSET
-#define LPD_XPPU_CFG_APERPERM_180_OFFSET 0XFF9812D0
-#undef LPD_XPPU_CFG_APERPERM_181_OFFSET
-#define LPD_XPPU_CFG_APERPERM_181_OFFSET 0XFF9812D4
-#undef LPD_XPPU_CFG_APERPERM_182_OFFSET
-#define LPD_XPPU_CFG_APERPERM_182_OFFSET 0XFF9812D8
-#undef LPD_XPPU_CFG_APERPERM_183_OFFSET
-#define LPD_XPPU_CFG_APERPERM_183_OFFSET 0XFF9812DC
-#undef LPD_XPPU_CFG_APERPERM_184_OFFSET
-#define LPD_XPPU_CFG_APERPERM_184_OFFSET 0XFF9812E0
-#undef LPD_XPPU_CFG_APERPERM_185_OFFSET
-#define LPD_XPPU_CFG_APERPERM_185_OFFSET 0XFF9812E4
-#undef LPD_XPPU_CFG_APERPERM_186_OFFSET
-#define LPD_XPPU_CFG_APERPERM_186_OFFSET 0XFF9812E8
-#undef LPD_XPPU_CFG_APERPERM_187_OFFSET
-#define LPD_XPPU_CFG_APERPERM_187_OFFSET 0XFF9812EC
-#undef LPD_XPPU_CFG_APERPERM_188_OFFSET
-#define LPD_XPPU_CFG_APERPERM_188_OFFSET 0XFF9812F0
-#undef LPD_XPPU_CFG_APERPERM_189_OFFSET
-#define LPD_XPPU_CFG_APERPERM_189_OFFSET 0XFF9812F4
-#undef LPD_XPPU_CFG_APERPERM_190_OFFSET
-#define LPD_XPPU_CFG_APERPERM_190_OFFSET 0XFF9812F8
-#undef LPD_XPPU_CFG_APERPERM_191_OFFSET
-#define LPD_XPPU_CFG_APERPERM_191_OFFSET 0XFF9812FC
-#undef LPD_XPPU_CFG_APERPERM_192_OFFSET
-#define LPD_XPPU_CFG_APERPERM_192_OFFSET 0XFF981300
-#undef LPD_XPPU_CFG_APERPERM_193_OFFSET
-#define LPD_XPPU_CFG_APERPERM_193_OFFSET 0XFF981304
-#undef LPD_XPPU_CFG_APERPERM_194_OFFSET
-#define LPD_XPPU_CFG_APERPERM_194_OFFSET 0XFF981308
-#undef LPD_XPPU_CFG_APERPERM_195_OFFSET
-#define LPD_XPPU_CFG_APERPERM_195_OFFSET 0XFF98130C
-#undef LPD_XPPU_CFG_APERPERM_196_OFFSET
-#define LPD_XPPU_CFG_APERPERM_196_OFFSET 0XFF981310
-#undef LPD_XPPU_CFG_APERPERM_197_OFFSET
-#define LPD_XPPU_CFG_APERPERM_197_OFFSET 0XFF981314
-#undef LPD_XPPU_CFG_APERPERM_198_OFFSET
-#define LPD_XPPU_CFG_APERPERM_198_OFFSET 0XFF981318
-#undef LPD_XPPU_CFG_APERPERM_199_OFFSET
-#define LPD_XPPU_CFG_APERPERM_199_OFFSET 0XFF98131C
-#undef LPD_XPPU_CFG_APERPERM_200_OFFSET
-#define LPD_XPPU_CFG_APERPERM_200_OFFSET 0XFF981320
-#undef LPD_XPPU_CFG_APERPERM_201_OFFSET
-#define LPD_XPPU_CFG_APERPERM_201_OFFSET 0XFF981324
-#undef LPD_XPPU_CFG_APERPERM_202_OFFSET
-#define LPD_XPPU_CFG_APERPERM_202_OFFSET 0XFF981328
-#undef LPD_XPPU_CFG_APERPERM_203_OFFSET
-#define LPD_XPPU_CFG_APERPERM_203_OFFSET 0XFF98132C
-#undef LPD_XPPU_CFG_APERPERM_204_OFFSET
-#define LPD_XPPU_CFG_APERPERM_204_OFFSET 0XFF981330
-#undef LPD_XPPU_CFG_APERPERM_205_OFFSET
-#define LPD_XPPU_CFG_APERPERM_205_OFFSET 0XFF981334
-#undef LPD_XPPU_CFG_APERPERM_206_OFFSET
-#define LPD_XPPU_CFG_APERPERM_206_OFFSET 0XFF981338
-#undef LPD_XPPU_CFG_APERPERM_207_OFFSET
-#define LPD_XPPU_CFG_APERPERM_207_OFFSET 0XFF98133C
-#undef LPD_XPPU_CFG_APERPERM_208_OFFSET
-#define LPD_XPPU_CFG_APERPERM_208_OFFSET 0XFF981340
-#undef LPD_XPPU_CFG_APERPERM_209_OFFSET
-#define LPD_XPPU_CFG_APERPERM_209_OFFSET 0XFF981344
-#undef LPD_XPPU_CFG_APERPERM_210_OFFSET
-#define LPD_XPPU_CFG_APERPERM_210_OFFSET 0XFF981348
-#undef LPD_XPPU_CFG_APERPERM_211_OFFSET
-#define LPD_XPPU_CFG_APERPERM_211_OFFSET 0XFF98134C
-#undef LPD_XPPU_CFG_APERPERM_212_OFFSET
-#define LPD_XPPU_CFG_APERPERM_212_OFFSET 0XFF981350
-#undef LPD_XPPU_CFG_APERPERM_213_OFFSET
-#define LPD_XPPU_CFG_APERPERM_213_OFFSET 0XFF981354
-#undef LPD_XPPU_CFG_APERPERM_214_OFFSET
-#define LPD_XPPU_CFG_APERPERM_214_OFFSET 0XFF981358
-#undef LPD_XPPU_CFG_APERPERM_215_OFFSET
-#define LPD_XPPU_CFG_APERPERM_215_OFFSET 0XFF98135C
-#undef LPD_XPPU_CFG_APERPERM_216_OFFSET
-#define LPD_XPPU_CFG_APERPERM_216_OFFSET 0XFF981360
-#undef LPD_XPPU_CFG_APERPERM_217_OFFSET
-#define LPD_XPPU_CFG_APERPERM_217_OFFSET 0XFF981364
-#undef LPD_XPPU_CFG_APERPERM_218_OFFSET
-#define LPD_XPPU_CFG_APERPERM_218_OFFSET 0XFF981368
-#undef LPD_XPPU_CFG_APERPERM_219_OFFSET
-#define LPD_XPPU_CFG_APERPERM_219_OFFSET 0XFF98136C
-#undef LPD_XPPU_CFG_APERPERM_220_OFFSET
-#define LPD_XPPU_CFG_APERPERM_220_OFFSET 0XFF981370
-#undef LPD_XPPU_CFG_APERPERM_221_OFFSET
-#define LPD_XPPU_CFG_APERPERM_221_OFFSET 0XFF981374
-#undef LPD_XPPU_CFG_APERPERM_222_OFFSET
-#define LPD_XPPU_CFG_APERPERM_222_OFFSET 0XFF981378
-#undef LPD_XPPU_CFG_APERPERM_223_OFFSET
-#define LPD_XPPU_CFG_APERPERM_223_OFFSET 0XFF98137C
-#undef LPD_XPPU_CFG_APERPERM_224_OFFSET
-#define LPD_XPPU_CFG_APERPERM_224_OFFSET 0XFF981380
-#undef LPD_XPPU_CFG_APERPERM_225_OFFSET
-#define LPD_XPPU_CFG_APERPERM_225_OFFSET 0XFF981384
-#undef LPD_XPPU_CFG_APERPERM_226_OFFSET
-#define LPD_XPPU_CFG_APERPERM_226_OFFSET 0XFF981388
-#undef LPD_XPPU_CFG_APERPERM_227_OFFSET
-#define LPD_XPPU_CFG_APERPERM_227_OFFSET 0XFF98138C
-#undef LPD_XPPU_CFG_APERPERM_228_OFFSET
-#define LPD_XPPU_CFG_APERPERM_228_OFFSET 0XFF981390
-#undef LPD_XPPU_CFG_APERPERM_229_OFFSET
-#define LPD_XPPU_CFG_APERPERM_229_OFFSET 0XFF981394
-#undef LPD_XPPU_CFG_APERPERM_230_OFFSET
-#define LPD_XPPU_CFG_APERPERM_230_OFFSET 0XFF981398
-#undef LPD_XPPU_CFG_APERPERM_231_OFFSET
-#define LPD_XPPU_CFG_APERPERM_231_OFFSET 0XFF98139C
-#undef LPD_XPPU_CFG_APERPERM_232_OFFSET
-#define LPD_XPPU_CFG_APERPERM_232_OFFSET 0XFF9813A0
-#undef LPD_XPPU_CFG_APERPERM_233_OFFSET
-#define LPD_XPPU_CFG_APERPERM_233_OFFSET 0XFF9813A4
-#undef LPD_XPPU_CFG_APERPERM_234_OFFSET
-#define LPD_XPPU_CFG_APERPERM_234_OFFSET 0XFF9813A8
-#undef LPD_XPPU_CFG_APERPERM_235_OFFSET
-#define LPD_XPPU_CFG_APERPERM_235_OFFSET 0XFF9813AC
-#undef LPD_XPPU_CFG_APERPERM_236_OFFSET
-#define LPD_XPPU_CFG_APERPERM_236_OFFSET 0XFF9813B0
-#undef LPD_XPPU_CFG_APERPERM_237_OFFSET
-#define LPD_XPPU_CFG_APERPERM_237_OFFSET 0XFF9813B4
-#undef LPD_XPPU_CFG_APERPERM_238_OFFSET
-#define LPD_XPPU_CFG_APERPERM_238_OFFSET 0XFF9813B8
-#undef LPD_XPPU_CFG_APERPERM_239_OFFSET
-#define LPD_XPPU_CFG_APERPERM_239_OFFSET 0XFF9813BC
-#undef LPD_XPPU_CFG_APERPERM_240_OFFSET
-#define LPD_XPPU_CFG_APERPERM_240_OFFSET 0XFF9813C0
-#undef LPD_XPPU_CFG_APERPERM_241_OFFSET
-#define LPD_XPPU_CFG_APERPERM_241_OFFSET 0XFF9813C4
-#undef LPD_XPPU_CFG_APERPERM_242_OFFSET
-#define LPD_XPPU_CFG_APERPERM_242_OFFSET 0XFF9813C8
-#undef LPD_XPPU_CFG_APERPERM_243_OFFSET
-#define LPD_XPPU_CFG_APERPERM_243_OFFSET 0XFF9813CC
-#undef LPD_XPPU_CFG_APERPERM_244_OFFSET
-#define LPD_XPPU_CFG_APERPERM_244_OFFSET 0XFF9813D0
-#undef LPD_XPPU_CFG_APERPERM_245_OFFSET
-#define LPD_XPPU_CFG_APERPERM_245_OFFSET 0XFF9813D4
-#undef LPD_XPPU_CFG_APERPERM_246_OFFSET
-#define LPD_XPPU_CFG_APERPERM_246_OFFSET 0XFF9813D8
-#undef LPD_XPPU_CFG_APERPERM_247_OFFSET
-#define LPD_XPPU_CFG_APERPERM_247_OFFSET 0XFF9813DC
-#undef LPD_XPPU_CFG_APERPERM_248_OFFSET
-#define LPD_XPPU_CFG_APERPERM_248_OFFSET 0XFF9813E0
-#undef LPD_XPPU_CFG_APERPERM_249_OFFSET
-#define LPD_XPPU_CFG_APERPERM_249_OFFSET 0XFF9813E4
-#undef LPD_XPPU_CFG_APERPERM_250_OFFSET
-#define LPD_XPPU_CFG_APERPERM_250_OFFSET 0XFF9813E8
-#undef LPD_XPPU_CFG_APERPERM_251_OFFSET
-#define LPD_XPPU_CFG_APERPERM_251_OFFSET 0XFF9813EC
-#undef LPD_XPPU_CFG_APERPERM_252_OFFSET
-#define LPD_XPPU_CFG_APERPERM_252_OFFSET 0XFF9813F0
#undef LPD_XPPU_CFG_APERPERM_256_OFFSET
#define LPD_XPPU_CFG_APERPERM_256_OFFSET 0XFF981400
#undef LPD_XPPU_CFG_APERPERM_257_OFFSET
#define LPD_XPPU_CFG_APERPERM_308_OFFSET 0XFF9814D0
#undef LPD_XPPU_CFG_APERPERM_309_OFFSET
#define LPD_XPPU_CFG_APERPERM_309_OFFSET 0XFF9814D4
-#undef LPD_XPPU_CFG_APERPERM_310_OFFSET
-#define LPD_XPPU_CFG_APERPERM_310_OFFSET 0XFF9814D8
-#undef LPD_XPPU_CFG_APERPERM_311_OFFSET
-#define LPD_XPPU_CFG_APERPERM_311_OFFSET 0XFF9814DC
-#undef LPD_XPPU_CFG_APERPERM_312_OFFSET
-#define LPD_XPPU_CFG_APERPERM_312_OFFSET 0XFF9814E0
-#undef LPD_XPPU_CFG_APERPERM_313_OFFSET
-#define LPD_XPPU_CFG_APERPERM_313_OFFSET 0XFF9814E4
-#undef LPD_XPPU_CFG_APERPERM_314_OFFSET
-#define LPD_XPPU_CFG_APERPERM_314_OFFSET 0XFF9814E8
-#undef LPD_XPPU_CFG_APERPERM_315_OFFSET
-#define LPD_XPPU_CFG_APERPERM_315_OFFSET 0XFF9814EC
-#undef LPD_XPPU_CFG_APERPERM_316_OFFSET
-#define LPD_XPPU_CFG_APERPERM_316_OFFSET 0XFF9814F0
-#undef LPD_XPPU_CFG_APERPERM_317_OFFSET
-#define LPD_XPPU_CFG_APERPERM_317_OFFSET 0XFF9814F4
#undef LPD_XPPU_CFG_APERPERM_318_OFFSET
#define LPD_XPPU_CFG_APERPERM_318_OFFSET 0XFF9814F8
#undef LPD_XPPU_CFG_APERPERM_319_OFFSET
#define LPD_XPPU_CFG_APERPERM_324_OFFSET 0XFF981510
#undef LPD_XPPU_CFG_APERPERM_325_OFFSET
#define LPD_XPPU_CFG_APERPERM_325_OFFSET 0XFF981514
-#undef LPD_XPPU_CFG_APERPERM_326_OFFSET
-#define LPD_XPPU_CFG_APERPERM_326_OFFSET 0XFF981518
-#undef LPD_XPPU_CFG_APERPERM_327_OFFSET
-#define LPD_XPPU_CFG_APERPERM_327_OFFSET 0XFF98151C
-#undef LPD_XPPU_CFG_APERPERM_328_OFFSET
-#define LPD_XPPU_CFG_APERPERM_328_OFFSET 0XFF981520
-#undef LPD_XPPU_CFG_APERPERM_329_OFFSET
-#define LPD_XPPU_CFG_APERPERM_329_OFFSET 0XFF981524
-#undef LPD_XPPU_CFG_APERPERM_330_OFFSET
-#define LPD_XPPU_CFG_APERPERM_330_OFFSET 0XFF981528
-#undef LPD_XPPU_CFG_APERPERM_331_OFFSET
-#define LPD_XPPU_CFG_APERPERM_331_OFFSET 0XFF98152C
-#undef LPD_XPPU_CFG_APERPERM_332_OFFSET
-#define LPD_XPPU_CFG_APERPERM_332_OFFSET 0XFF981530
-#undef LPD_XPPU_CFG_APERPERM_333_OFFSET
-#define LPD_XPPU_CFG_APERPERM_333_OFFSET 0XFF981534
#undef LPD_XPPU_CFG_APERPERM_334_OFFSET
#define LPD_XPPU_CFG_APERPERM_334_OFFSET 0XFF981538
#undef LPD_XPPU_CFG_APERPERM_335_OFFSET
#define LPD_XPPU_CFG_APERPERM_340_OFFSET 0XFF981550
#undef LPD_XPPU_CFG_APERPERM_341_OFFSET
#define LPD_XPPU_CFG_APERPERM_341_OFFSET 0XFF981554
-#undef LPD_XPPU_CFG_APERPERM_342_OFFSET
-#define LPD_XPPU_CFG_APERPERM_342_OFFSET 0XFF981558
-#undef LPD_XPPU_CFG_APERPERM_343_OFFSET
-#define LPD_XPPU_CFG_APERPERM_343_OFFSET 0XFF98155C
-#undef LPD_XPPU_CFG_APERPERM_344_OFFSET
-#define LPD_XPPU_CFG_APERPERM_344_OFFSET 0XFF981560
-#undef LPD_XPPU_CFG_APERPERM_345_OFFSET
-#define LPD_XPPU_CFG_APERPERM_345_OFFSET 0XFF981564
-#undef LPD_XPPU_CFG_APERPERM_346_OFFSET
-#define LPD_XPPU_CFG_APERPERM_346_OFFSET 0XFF981568
-#undef LPD_XPPU_CFG_APERPERM_347_OFFSET
-#define LPD_XPPU_CFG_APERPERM_347_OFFSET 0XFF98156C
-#undef LPD_XPPU_CFG_APERPERM_348_OFFSET
-#define LPD_XPPU_CFG_APERPERM_348_OFFSET 0XFF981570
-#undef LPD_XPPU_CFG_APERPERM_349_OFFSET
-#define LPD_XPPU_CFG_APERPERM_349_OFFSET 0XFF981574
#undef LPD_XPPU_CFG_APERPERM_350_OFFSET
#define LPD_XPPU_CFG_APERPERM_350_OFFSET 0XFF981578
#undef LPD_XPPU_CFG_APERPERM_351_OFFSET
#define LPD_XPPU_CFG_APERPERM_356_OFFSET 0XFF981590
#undef LPD_XPPU_CFG_APERPERM_357_OFFSET
#define LPD_XPPU_CFG_APERPERM_357_OFFSET 0XFF981594
-#undef LPD_XPPU_CFG_APERPERM_358_OFFSET
-#define LPD_XPPU_CFG_APERPERM_358_OFFSET 0XFF981598
-#undef LPD_XPPU_CFG_APERPERM_359_OFFSET
-#define LPD_XPPU_CFG_APERPERM_359_OFFSET 0XFF98159C
-#undef LPD_XPPU_CFG_APERPERM_360_OFFSET
-#define LPD_XPPU_CFG_APERPERM_360_OFFSET 0XFF9815A0
-#undef LPD_XPPU_CFG_APERPERM_361_OFFSET
-#define LPD_XPPU_CFG_APERPERM_361_OFFSET 0XFF9815A4
-#undef LPD_XPPU_CFG_APERPERM_362_OFFSET
-#define LPD_XPPU_CFG_APERPERM_362_OFFSET 0XFF9815A8
-#undef LPD_XPPU_CFG_APERPERM_363_OFFSET
-#define LPD_XPPU_CFG_APERPERM_363_OFFSET 0XFF9815AC
-#undef LPD_XPPU_CFG_APERPERM_364_OFFSET
-#define LPD_XPPU_CFG_APERPERM_364_OFFSET 0XFF9815B0
-#undef LPD_XPPU_CFG_APERPERM_365_OFFSET
-#define LPD_XPPU_CFG_APERPERM_365_OFFSET 0XFF9815B4
#undef LPD_XPPU_CFG_APERPERM_366_OFFSET
#define LPD_XPPU_CFG_APERPERM_366_OFFSET 0XFF9815B8
#undef LPD_XPPU_CFG_APERPERM_367_OFFSET
#define LPD_XPPU_CFG_APERPERM_382_OFFSET 0XFF9815F8
#undef LPD_XPPU_CFG_APERPERM_383_OFFSET
#define LPD_XPPU_CFG_APERPERM_383_OFFSET 0XFF9815FC
-#undef LPD_XPPU_CFG_APERPERM_384_OFFSET
-#define LPD_XPPU_CFG_APERPERM_384_OFFSET 0XFF981600
-#undef LPD_XPPU_CFG_APERPERM_385_OFFSET
-#define LPD_XPPU_CFG_APERPERM_385_OFFSET 0XFF981604
-#undef LPD_XPPU_CFG_APERPERM_386_OFFSET
-#define LPD_XPPU_CFG_APERPERM_386_OFFSET 0XFF981608
-#undef LPD_XPPU_CFG_APERPERM_387_OFFSET
-#define LPD_XPPU_CFG_APERPERM_387_OFFSET 0XFF98160C
-#undef LPD_XPPU_CFG_APERPERM_388_OFFSET
-#define LPD_XPPU_CFG_APERPERM_388_OFFSET 0XFF981610
-#undef LPD_XPPU_CFG_APERPERM_389_OFFSET
-#define LPD_XPPU_CFG_APERPERM_389_OFFSET 0XFF981614
-#undef LPD_XPPU_CFG_APERPERM_390_OFFSET
-#define LPD_XPPU_CFG_APERPERM_390_OFFSET 0XFF981618
-#undef LPD_XPPU_CFG_APERPERM_391_OFFSET
-#define LPD_XPPU_CFG_APERPERM_391_OFFSET 0XFF98161C
-#undef LPD_XPPU_CFG_APERPERM_392_OFFSET
-#define LPD_XPPU_CFG_APERPERM_392_OFFSET 0XFF981620
-#undef LPD_XPPU_CFG_APERPERM_393_OFFSET
-#define LPD_XPPU_CFG_APERPERM_393_OFFSET 0XFF981624
-#undef LPD_XPPU_CFG_APERPERM_394_OFFSET
-#define LPD_XPPU_CFG_APERPERM_394_OFFSET 0XFF981628
-#undef LPD_XPPU_CFG_APERPERM_395_OFFSET
-#define LPD_XPPU_CFG_APERPERM_395_OFFSET 0XFF98162C
-#undef LPD_XPPU_CFG_APERPERM_396_OFFSET
-#define LPD_XPPU_CFG_APERPERM_396_OFFSET 0XFF981630
-#undef LPD_XPPU_CFG_APERPERM_397_OFFSET
-#define LPD_XPPU_CFG_APERPERM_397_OFFSET 0XFF981634
-#undef LPD_XPPU_CFG_APERPERM_398_OFFSET
-#define LPD_XPPU_CFG_APERPERM_398_OFFSET 0XFF981638
-#undef LPD_XPPU_CFG_APERPERM_399_OFFSET
-#define LPD_XPPU_CFG_APERPERM_399_OFFSET 0XFF98163C
-#undef LPD_XPPU_CFG_APERPERM_400_OFFSET
-#define LPD_XPPU_CFG_APERPERM_400_OFFSET 0XFF981640
+#undef LPD_XPPU_SINK_ERR_CTRL_OFFSET
+#define LPD_XPPU_SINK_ERR_CTRL_OFFSET 0XFF9CFFEC
#undef LPD_XPPU_CFG_CTRL_OFFSET
#define LPD_XPPU_CFG_CTRL_OFFSET 0XFF980000
+#undef LPD_XPPU_CFG_IEN_OFFSET
+#define LPD_XPPU_CFG_IEN_OFFSET 0XFF980018
/*If set, only read transactions are allowed for the masters matching this register*/
#undef LPD_XPPU_CFG_MASTER_ID00_MIDR_DEFVAL
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_000_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_000_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_000_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_000_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_000_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_000_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_048_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_000_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_000_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_000_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_000_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_000_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_000_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_000_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_000_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_000_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_000_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_000_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_000_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_048_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_048_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_048_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_048_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_001_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_001_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_001_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_001_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_001_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_001_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_049_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_001_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_001_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_001_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_001_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_001_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_001_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_001_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_001_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_001_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_001_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_001_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_001_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_049_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_049_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_049_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_049_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_002_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_002_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_002_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_002_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_002_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_002_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_050_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_002_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_002_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_002_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_002_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_002_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_002_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_002_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_002_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_002_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_002_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_002_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_002_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_050_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_050_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_050_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_050_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_003_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_003_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_003_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_003_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_003_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_003_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_051_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_003_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_003_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_003_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_003_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_003_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_003_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_003_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_003_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_003_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_003_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_003_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_003_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_051_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_051_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_051_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_051_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_004_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_004_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_004_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_004_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_004_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_004_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_256_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_004_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_004_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_004_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_004_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_004_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_004_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_004_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_004_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_004_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_004_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_004_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_004_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_256_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_256_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_256_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_256_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_005_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_005_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_005_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_005_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_005_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_005_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_257_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_005_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_005_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_005_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_005_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_005_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_005_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_005_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_005_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_005_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_005_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_005_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_005_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_257_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_257_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_257_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_257_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_006_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_006_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_006_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_006_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_006_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_006_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_258_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_006_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_006_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_006_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_006_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_006_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_006_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_006_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_006_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_006_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_006_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_006_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_006_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_258_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_258_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_258_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_258_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_007_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_007_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_007_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_007_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_007_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_007_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_259_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_007_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_007_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_007_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_007_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_007_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_007_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_007_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_007_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_007_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_007_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_007_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_007_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_259_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_259_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_259_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_259_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_008_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_008_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_008_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_008_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_008_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_008_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_260_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_008_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_008_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_008_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_008_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_008_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_008_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_008_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_008_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_008_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_008_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_008_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_008_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_260_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_260_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_260_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_260_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_009_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_009_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_009_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_009_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_009_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_009_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_261_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_009_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_009_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_009_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_009_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_009_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_009_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_009_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_009_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_009_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_009_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_009_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_009_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_261_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_261_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_261_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_261_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_010_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_010_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_010_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_010_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_010_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_010_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_262_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_010_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_010_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_010_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_010_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_010_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_010_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_010_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_010_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_010_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_010_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_010_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_010_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_262_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_262_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_262_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_262_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_011_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_011_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_011_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_011_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_011_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_011_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_263_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_011_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_011_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_011_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_011_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_011_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_011_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_011_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_011_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_011_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_011_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_011_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_011_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_263_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_263_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_263_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_263_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_012_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_012_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_012_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_012_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_012_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_012_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_264_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_012_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_012_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_012_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_012_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_012_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_012_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_012_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_012_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_012_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_012_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_012_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_012_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_264_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_264_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_264_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_264_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_013_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_013_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_013_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_013_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_013_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_013_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_265_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_013_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_013_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_013_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_013_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_013_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_013_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_013_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_013_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_013_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_013_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_013_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_013_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_014_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_014_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_014_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_014_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_014_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_014_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_014_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_014_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_014_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_014_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_014_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_014_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_014_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_014_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_014_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_014_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_014_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_014_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_015_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_015_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_015_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_015_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_015_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_015_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_015_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_015_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_015_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_015_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_015_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_015_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_015_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_015_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_015_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_015_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_015_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_015_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_016_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_016_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_016_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_016_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_016_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_016_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_016_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_016_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_016_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_016_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_016_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_016_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_016_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_016_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_016_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_016_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_016_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_016_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_017_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_017_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_017_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_017_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_017_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_017_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_017_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_017_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_017_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_017_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_017_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_017_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_017_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_017_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_017_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_017_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_017_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_017_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_018_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_018_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_018_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_018_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_018_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_018_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_018_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_018_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_018_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_018_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_018_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_018_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_018_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_018_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_018_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_018_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_018_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_018_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_019_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_019_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_019_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_019_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_019_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_019_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_019_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_019_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_019_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_019_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_019_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_019_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_019_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_019_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_019_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_019_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_019_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_019_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_020_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_020_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_020_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_020_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_020_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_020_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_020_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_020_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_020_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_020_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_020_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_020_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_020_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_020_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_020_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_020_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_020_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_020_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_021_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_021_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_021_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_021_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_021_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_021_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_021_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_021_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_021_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_021_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_021_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_021_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_021_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_021_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_021_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_021_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_021_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_021_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_022_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_022_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_022_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_022_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_022_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_022_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_022_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_022_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_022_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_022_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_022_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_022_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_022_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_022_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_022_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_022_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_022_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_022_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_023_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_023_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_023_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_023_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_023_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_023_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_023_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_023_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_023_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_023_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_023_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_023_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_023_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_023_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_023_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_023_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_023_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_023_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_024_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_024_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_024_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_024_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_024_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_024_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_024_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_024_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_024_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_024_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_024_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_024_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_024_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_024_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_024_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_024_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_024_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_024_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_025_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_025_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_025_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_025_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_025_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_025_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_025_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_025_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_025_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_025_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_025_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_025_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_025_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_025_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_025_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_025_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_025_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_025_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_026_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_026_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_026_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_026_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_026_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_026_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_026_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_026_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_026_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_026_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_026_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_026_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_026_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_026_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_026_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_026_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_026_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_026_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_027_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_027_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_027_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_027_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_027_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_027_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_027_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_027_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_027_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_027_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_027_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_027_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_027_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_027_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_027_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_027_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_027_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_027_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_028_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_028_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_028_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_028_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_028_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_028_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_028_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_028_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_028_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_028_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_028_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_028_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_028_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_028_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_028_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_028_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_028_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_028_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_029_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_029_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_029_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_029_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_029_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_029_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_029_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_029_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_029_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_029_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_029_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_029_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_029_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_029_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_029_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_029_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_029_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_029_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_030_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_030_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_030_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_030_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_030_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_030_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_030_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_030_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_030_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_030_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_030_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_030_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_030_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_030_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_030_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_030_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_030_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_030_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_031_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_031_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_031_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_031_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_031_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_031_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_031_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_031_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_031_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_031_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_031_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_031_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_031_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_031_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_031_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_031_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_031_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_031_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_032_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_032_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_032_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_032_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_032_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_032_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_032_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_032_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_032_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_032_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_032_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_032_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_032_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_032_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_032_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_032_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_032_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_032_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_033_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_033_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_033_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_033_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_033_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_033_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_033_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_033_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_033_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_033_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_033_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_033_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_033_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_033_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_033_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_033_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_033_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_033_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_034_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_034_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_034_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_034_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_034_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_034_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_034_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_034_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_034_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_034_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_034_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_034_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_034_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_034_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_034_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_034_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_034_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_034_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_035_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_035_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_035_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_035_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_035_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_035_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_035_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_035_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_035_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_035_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_035_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_035_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_035_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_035_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_035_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_035_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_035_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_035_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_036_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_036_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_036_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_036_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_036_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_036_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_036_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_036_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_036_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_036_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_036_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_036_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_036_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_036_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_036_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_036_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_036_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_036_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_037_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_037_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_037_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_037_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_037_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_037_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_037_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_037_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_037_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_037_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_037_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_037_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_037_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_037_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_037_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_037_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_037_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_037_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_038_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_038_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_038_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_038_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_038_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_038_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_038_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_038_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_038_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_038_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_038_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_038_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_038_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_038_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_038_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_038_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_038_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_038_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_039_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_039_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_039_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_039_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_039_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_039_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_039_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_039_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_039_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_039_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_039_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_039_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_039_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_039_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_039_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_039_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_039_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_039_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_040_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_040_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_040_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_040_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_040_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_040_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_040_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_040_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_040_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_040_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_040_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_040_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_040_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_040_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_040_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_040_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_040_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_040_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_041_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_041_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_041_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_041_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_041_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_041_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_041_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_041_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_041_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_041_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_041_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_041_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_041_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_041_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_041_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_041_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_041_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_041_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_042_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_042_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_042_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_042_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_042_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_042_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_042_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_042_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_042_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_042_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_042_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_042_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_042_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_042_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_042_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_042_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_042_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_042_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_043_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_043_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_043_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_043_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_043_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_043_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_043_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_043_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_043_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_043_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_043_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_043_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_043_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_043_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_043_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_043_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_043_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_043_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_044_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_044_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_044_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_044_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_044_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_044_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_044_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_044_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_044_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_044_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_044_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_044_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_044_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_044_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_044_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_044_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_044_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_044_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_045_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_045_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_045_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_045_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_045_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_045_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_045_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_045_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_045_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_045_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_045_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_045_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_045_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_045_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_045_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_045_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_045_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_045_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_046_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_046_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_046_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_046_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_046_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_046_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_046_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_046_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_046_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_046_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_046_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_046_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_046_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_046_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_046_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_046_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_046_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_046_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_047_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_047_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_047_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_047_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_047_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_047_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_047_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_047_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_047_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_047_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_047_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_047_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_047_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_047_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_047_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_047_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_047_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_047_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_048_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_048_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_048_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_048_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_048_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_048_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_048_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_048_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_048_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_049_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_049_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_049_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_049_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_049_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_049_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_049_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_049_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_049_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_050_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_050_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_050_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_050_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_050_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_050_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_050_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_050_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_050_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_051_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_051_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_051_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_051_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_051_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_051_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_051_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_051_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_051_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_052_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_052_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_052_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_052_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_052_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_052_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_052_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_052_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_052_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_052_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_052_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_052_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_052_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_052_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_052_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_052_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_052_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_052_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_053_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_053_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_053_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_053_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_053_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_053_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_053_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_053_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_053_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_053_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_053_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_053_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_053_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_053_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_053_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_053_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_053_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_053_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_054_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_054_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_054_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_054_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_054_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_054_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_054_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_054_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_054_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_054_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_054_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_054_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_054_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_054_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_054_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_054_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_054_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_054_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_055_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_055_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_055_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_055_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_055_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_055_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_055_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_055_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_055_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_055_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_055_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_055_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_055_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_055_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_055_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_055_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_055_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_055_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_056_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_056_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_056_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_056_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_056_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_056_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_056_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_056_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_056_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_056_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_056_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_056_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_056_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_056_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_056_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_056_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_056_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_056_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_057_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_057_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_057_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_057_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_057_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_057_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_057_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_057_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_057_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_057_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_057_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_057_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_057_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_057_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_057_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_057_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_057_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_057_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_058_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_058_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_058_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_058_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_058_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_058_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_058_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_058_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_058_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_058_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_058_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_058_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_058_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_058_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_058_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_058_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_058_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_058_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_059_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_059_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_059_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_059_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_059_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_059_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_059_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_059_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_059_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_059_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_059_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_059_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_059_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_059_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_059_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_059_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_059_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_059_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_060_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_060_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_060_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_060_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_060_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_060_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_060_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_060_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_060_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_060_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_060_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_060_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_060_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_060_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_060_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_060_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_060_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_060_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_061_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_061_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_061_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_061_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_061_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_061_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_061_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_061_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_061_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_061_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_061_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_061_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_061_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_061_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_061_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_061_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_061_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_061_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_062_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_062_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_062_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_062_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_062_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_062_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_062_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_062_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_062_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_062_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_062_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_062_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_062_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_062_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_062_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_062_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_062_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_062_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_063_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_063_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_063_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_063_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_063_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_063_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_063_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_063_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_063_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_063_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_063_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_063_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_063_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_063_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_063_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_063_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_063_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_063_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_064_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_064_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_064_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_064_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_064_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_064_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_064_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_064_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_064_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_064_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_064_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_064_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_064_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_064_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_064_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_064_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_064_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_064_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_065_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_065_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_065_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_065_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_065_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_065_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_065_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_065_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_065_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_065_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_065_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_065_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_065_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_065_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_065_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_065_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_065_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_065_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_066_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_066_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_066_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_066_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_066_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_066_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_066_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_066_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_066_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_066_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_066_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_066_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_066_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_066_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_066_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_066_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_066_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_066_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_067_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_067_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_067_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_067_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_067_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_067_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_067_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_067_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_067_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_067_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_067_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_067_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_067_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_067_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_067_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_067_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_067_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_067_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_068_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_068_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_068_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_068_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_068_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_068_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_068_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_068_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_068_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_068_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_068_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_068_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_068_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_068_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_068_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_068_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_068_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_068_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_069_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_069_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_069_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_069_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_069_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_069_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_069_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_069_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_069_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_069_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_069_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_069_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_069_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_069_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_069_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_069_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_069_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_069_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_070_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_070_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_070_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_070_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_070_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_070_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_070_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_070_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_070_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_070_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_070_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_070_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_070_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_070_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_070_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_070_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_070_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_070_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_071_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_071_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_071_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_071_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_071_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_071_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_071_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_071_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_071_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_071_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_071_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_071_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_071_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_071_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_071_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_071_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_071_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_071_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_072_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_072_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_072_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_072_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_072_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_072_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_072_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_072_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_072_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_072_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_072_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_072_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_072_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_072_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_072_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_072_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_072_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_072_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_073_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_073_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_073_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_073_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_073_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_073_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_073_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_073_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_073_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_073_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_073_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_073_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_073_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_073_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_073_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_073_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_073_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_073_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_074_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_074_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_074_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_074_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_074_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_074_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_074_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_074_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_074_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_074_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_074_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_074_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_074_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_074_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_074_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_074_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_074_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_074_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_075_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_075_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_075_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_075_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_075_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_075_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_075_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_075_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_075_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_075_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_075_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_075_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_075_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_075_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_075_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_075_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_075_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_075_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_076_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_076_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_076_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_076_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_076_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_076_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_076_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_076_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_076_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_076_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_076_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_076_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_076_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_076_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_076_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_076_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_076_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_076_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_077_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_077_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_077_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_077_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_077_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_077_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_077_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_077_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_077_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_077_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_077_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_077_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_077_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_077_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_077_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_077_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_077_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_077_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_078_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_078_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_078_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_078_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_078_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_078_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_078_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_078_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_078_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_078_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_078_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_078_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_078_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_078_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_078_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_078_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_078_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_078_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_079_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_079_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_079_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_079_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_079_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_079_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_079_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_079_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_079_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_079_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_079_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_079_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_079_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_079_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_079_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_079_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_079_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_079_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_080_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_080_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_080_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_080_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_080_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_080_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_080_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_080_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_080_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_080_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_080_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_080_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_080_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_080_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_080_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_080_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_080_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_080_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_081_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_081_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_081_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_081_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_081_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_081_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_081_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_081_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_081_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_081_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_081_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_081_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_081_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_081_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_081_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_081_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_081_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_081_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_082_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_082_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_082_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_082_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_082_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_082_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_082_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_082_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_082_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_082_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_082_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_082_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_082_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_082_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_082_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_082_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_082_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_082_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_083_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_083_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_083_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_083_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_083_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_083_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_083_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_083_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_083_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_083_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_083_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_083_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_083_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_083_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_083_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_083_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_083_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_083_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_084_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_084_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_084_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_084_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_084_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_084_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_084_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_084_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_084_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_084_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_084_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_084_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_084_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_084_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_084_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_084_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_084_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_084_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_085_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_085_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_085_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_085_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_085_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_085_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_085_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_085_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_085_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_085_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_085_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_085_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_085_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_085_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_085_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_085_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_085_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_085_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_086_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_086_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_086_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_086_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_086_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_086_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_086_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_086_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_086_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_086_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_086_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_086_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_086_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_086_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_086_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_086_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_086_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_086_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_087_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_087_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_087_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_087_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_087_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_087_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_087_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_087_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_087_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_087_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_087_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_087_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_087_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_087_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_087_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_087_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_087_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_087_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_088_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_088_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_088_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_088_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_088_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_088_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_088_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_088_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_088_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_088_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_088_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_088_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_088_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_088_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_088_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_088_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_088_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_088_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_089_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_089_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_089_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_089_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_089_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_089_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_089_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_089_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_089_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_089_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_089_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_089_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_089_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_089_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_089_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_089_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_089_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_089_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_090_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_090_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_090_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_090_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_090_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_090_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_090_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_090_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_090_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_090_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_090_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_090_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_090_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_090_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_090_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_090_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_090_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_090_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_091_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_091_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_091_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_091_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_091_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_091_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_091_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_091_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_091_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_091_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_091_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_091_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_091_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_091_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_091_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_091_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_091_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_091_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_092_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_092_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_092_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_092_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_092_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_092_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_092_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_092_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_092_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_092_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_092_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_092_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_092_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_092_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_092_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_092_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_092_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_092_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_093_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_093_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_093_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_093_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_093_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_093_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_093_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_093_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_093_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_093_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_093_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_093_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_093_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_093_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_093_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_093_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_093_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_093_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_094_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_094_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_094_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_094_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_094_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_094_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_094_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_094_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_094_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_094_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_094_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_094_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_094_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_094_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_094_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_094_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_094_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_094_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_095_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_095_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_095_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_095_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_095_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_095_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_095_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_095_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_095_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_095_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_095_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_095_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_095_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_095_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_095_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_095_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_095_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_095_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_096_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_096_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_096_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_096_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_096_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_096_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_096_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_096_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_096_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_096_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_096_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_096_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_096_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_096_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_096_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_096_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_096_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_096_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_097_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_097_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_097_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_097_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_097_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_097_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_097_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_097_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_097_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_097_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_097_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_097_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_097_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_097_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_097_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_097_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_097_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_097_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_098_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_098_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_098_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_098_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_098_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_098_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_098_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_098_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_098_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_098_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_098_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_098_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_098_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_098_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_098_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_098_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_098_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_098_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_099_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_099_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_099_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_099_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_099_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_099_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_099_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_099_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_099_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_099_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_099_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_099_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_099_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_099_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_099_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_099_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_099_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_099_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_100_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_100_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_100_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_100_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_100_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_100_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_100_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_100_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_100_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_100_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_100_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_100_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_100_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_100_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_100_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_100_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_100_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_100_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_101_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_101_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_101_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_101_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_101_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_101_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_101_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_101_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_101_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_101_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_101_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_101_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_101_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_101_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_101_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_101_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_101_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_101_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_102_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_102_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_102_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_102_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_102_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_102_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_102_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_102_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_102_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_102_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_102_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_102_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_102_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_102_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_102_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_102_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_102_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_102_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_103_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_103_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_103_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_103_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_103_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_103_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_103_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_103_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_103_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_103_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_103_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_103_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_103_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_103_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_103_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_103_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_103_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_103_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_104_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_104_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_104_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_104_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_104_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_104_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_104_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_104_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_104_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_104_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_104_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_104_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_104_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_104_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_104_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_104_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_104_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_104_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_105_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_105_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_105_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_105_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_105_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_105_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_105_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_105_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_105_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_105_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_105_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_105_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_105_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_105_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_105_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_105_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_105_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_105_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_106_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_106_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_106_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_106_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_106_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_106_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_106_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_106_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_106_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_106_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_106_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_106_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_106_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_106_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_106_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_106_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_106_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_106_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_107_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_107_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_107_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_107_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_107_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_107_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_107_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_107_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_107_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_107_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_107_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_107_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_107_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_107_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_107_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_107_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_107_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_107_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_108_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_108_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_108_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_108_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_108_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_108_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_108_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_108_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_108_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_108_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_108_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_108_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_108_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_108_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_108_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_108_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_108_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_108_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_109_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_109_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_109_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_109_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_109_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_109_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_109_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_109_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_109_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_109_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_109_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_109_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_109_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_109_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_109_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_109_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_109_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_109_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_110_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_110_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_110_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_110_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_110_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_110_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_110_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_110_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_110_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_110_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_110_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_110_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_110_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_110_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_110_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_110_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_110_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_110_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_111_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_111_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_111_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_111_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_111_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_111_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_111_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_111_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_111_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_111_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_111_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_111_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_111_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_111_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_111_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_111_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_111_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_111_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_112_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_112_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_112_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_112_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_112_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_112_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_112_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_112_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_112_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_112_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_112_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_112_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_112_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_112_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_112_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_112_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_112_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_112_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_113_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_113_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_113_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_113_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_113_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_113_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_113_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_113_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_113_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_113_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_113_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_113_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_113_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_113_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_113_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_113_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_113_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_113_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_114_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_114_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_114_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_114_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_114_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_114_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_114_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_114_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_114_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_114_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_114_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_114_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_114_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_114_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_114_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_114_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_114_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_114_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_115_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_115_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_115_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_115_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_115_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_115_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_115_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_115_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_115_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_115_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_115_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_115_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_115_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_115_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_115_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_115_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_115_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_115_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_116_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_116_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_116_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_116_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_116_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_116_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_116_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_116_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_116_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_116_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_116_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_116_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_116_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_116_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_116_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_116_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_116_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_116_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_117_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_117_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_117_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_117_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_117_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_117_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_117_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_117_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_117_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_117_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_117_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_117_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_117_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_117_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_117_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_117_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_117_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_117_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_118_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_118_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_118_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_118_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_118_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_118_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_118_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_118_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_118_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_118_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_118_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_118_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_118_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_118_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_118_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_118_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_118_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_118_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_119_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_119_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_119_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_119_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_119_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_119_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_119_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_119_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_119_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_119_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_119_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_119_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_119_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_119_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_119_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_119_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_119_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_119_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_120_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_120_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_120_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_120_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_120_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_120_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_120_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_120_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_120_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_120_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_120_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_120_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_120_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_120_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_120_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_120_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_120_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_120_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_121_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_121_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_121_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_121_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_121_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_121_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_121_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_121_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_121_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_121_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_121_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_121_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_121_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_121_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_121_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_121_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_121_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_121_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_122_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_122_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_122_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_122_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_122_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_122_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_122_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_122_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_122_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_122_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_122_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_122_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_122_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_122_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_122_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_122_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_122_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_122_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_123_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_123_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_123_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_123_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_123_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_123_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_123_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_123_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_123_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_123_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_123_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_123_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_123_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_123_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_123_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_123_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_123_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_123_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_124_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_124_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_124_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_124_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_124_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_124_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_124_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_124_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_124_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_124_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_124_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_124_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_124_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_124_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_124_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_124_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_124_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_124_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_125_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_125_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_125_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_125_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_125_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_125_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_125_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_125_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_125_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_125_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_125_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_125_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_125_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_125_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_125_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_125_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_125_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_125_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_126_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_126_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_126_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_126_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_126_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_126_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_126_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_126_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_126_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_126_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_126_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_126_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_126_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_126_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_126_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_126_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_126_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_126_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_127_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_127_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_127_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_127_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_127_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_127_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_127_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_127_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_127_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_127_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_127_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_127_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_127_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_127_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_127_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_127_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_127_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_127_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_128_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_128_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_128_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_128_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_128_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_128_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_128_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_128_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_128_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_128_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_128_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_128_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_128_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_128_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_128_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_128_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_128_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_128_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_129_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_129_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_129_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_129_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_129_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_129_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_129_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_129_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_129_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_129_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_129_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_129_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_129_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_129_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_129_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_129_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_129_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_129_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_130_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_130_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_130_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_130_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_130_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_130_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_130_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_130_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_130_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_130_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_130_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_130_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_130_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_130_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_130_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_130_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_130_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_130_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_131_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_131_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_131_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_131_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_131_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_131_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_131_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_131_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_131_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_131_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_131_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_131_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_131_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_131_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_131_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_131_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_131_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_131_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_132_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_132_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_132_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_132_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_132_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_132_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_132_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_132_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_132_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_132_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_132_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_132_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_132_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_132_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_132_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_132_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_132_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_132_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_133_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_133_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_133_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_133_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_133_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_133_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_133_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_133_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_133_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_133_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_133_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_133_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_133_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_133_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_133_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_133_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_133_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_133_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_134_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_134_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_134_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_134_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_134_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_134_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_134_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_134_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_134_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_134_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_134_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_134_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_134_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_134_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_134_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_134_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_134_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_134_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_135_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_135_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_135_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_135_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_135_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_135_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_135_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_135_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_135_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_135_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_135_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_135_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_135_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_135_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_135_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_135_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_135_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_135_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_136_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_136_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_136_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_136_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_136_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_136_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_136_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_136_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_136_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_136_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_136_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_136_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_136_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_136_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_136_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_136_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_136_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_136_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_137_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_137_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_137_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_137_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_137_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_137_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_137_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_137_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_137_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_137_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_137_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_137_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_137_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_137_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_137_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_137_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_137_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_137_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_138_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_138_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_138_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_138_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_138_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_138_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_138_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_138_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_138_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_138_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_138_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_138_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_138_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_138_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_138_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_138_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_138_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_138_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_139_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_139_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_139_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_139_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_139_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_139_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_139_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_139_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_139_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_139_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_139_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_139_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_139_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_139_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_139_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_139_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_139_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_139_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_140_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_140_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_140_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_140_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_140_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_140_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_140_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_140_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_140_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_140_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_140_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_140_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_140_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_140_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_140_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_140_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_140_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_140_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_141_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_141_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_141_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_141_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_141_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_141_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_141_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_141_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_141_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_141_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_141_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_141_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_141_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_141_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_141_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_141_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_141_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_141_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_142_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_142_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_142_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_142_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_142_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_142_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_142_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_142_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_142_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_142_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_142_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_142_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_142_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_142_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_142_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_142_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_142_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_142_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_143_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_143_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_143_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_143_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_143_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_143_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_143_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_143_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_143_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_143_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_143_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_143_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_143_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_143_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_143_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_143_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_143_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_143_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_144_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_144_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_144_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_144_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_144_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_144_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_144_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_144_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_144_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_144_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_144_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_144_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_144_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_144_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_144_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_144_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_144_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_144_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_145_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_145_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_145_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_145_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_145_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_145_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_145_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_145_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_145_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_145_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_145_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_145_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_145_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_145_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_145_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_145_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_145_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_145_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_146_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_146_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_146_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_146_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_146_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_146_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_146_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_146_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_146_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_146_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_146_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_146_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_146_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_146_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_146_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_146_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_146_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_146_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_147_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_147_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_147_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_147_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_147_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_147_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_147_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_147_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_147_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_147_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_147_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_147_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_147_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_147_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_147_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_147_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_147_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_147_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_148_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_148_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_148_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_148_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_148_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_148_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_148_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_148_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_148_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_148_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_148_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_148_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_148_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_148_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_148_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_148_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_148_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_148_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_149_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_149_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_149_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_149_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_149_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_149_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_149_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_149_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_149_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_149_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_149_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_149_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_149_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_149_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_149_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_149_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_149_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_149_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_150_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_150_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_150_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_150_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_150_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_150_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_150_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_150_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_150_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_150_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_150_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_150_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_150_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_150_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_150_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_150_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_150_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_150_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_151_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_151_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_151_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_151_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_151_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_151_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_151_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_151_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_151_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_151_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_151_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_151_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_151_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_151_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_151_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_151_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_151_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_151_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_152_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_152_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_152_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_152_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_152_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_153_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_153_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_153_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_153_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_153_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_153_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_153_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_153_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_153_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_153_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_153_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_153_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_153_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_153_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_153_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_153_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_153_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_153_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_154_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_154_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_154_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_154_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_154_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_154_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_154_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_154_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_154_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_154_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_154_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_154_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_154_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_154_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_154_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_154_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_154_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_154_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_155_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_155_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_155_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_155_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_155_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_155_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_155_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_155_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_155_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_155_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_155_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_155_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_155_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_155_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_155_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_155_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_155_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_155_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_156_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_156_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_156_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_156_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_156_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_156_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_156_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_156_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_156_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_156_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_156_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_156_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_156_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_156_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_156_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_156_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_156_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_156_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_157_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_157_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_157_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_157_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_157_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_157_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_157_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_157_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_157_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_157_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_157_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_157_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_157_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_157_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_157_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_157_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_157_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_157_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_158_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_158_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_158_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_158_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_158_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_158_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_158_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_158_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_158_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_158_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_158_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_158_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_158_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_158_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_158_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_158_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_158_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_158_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_159_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_159_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_159_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_159_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_159_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_159_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_159_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_159_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_159_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_159_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_159_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_159_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_159_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_159_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_159_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_159_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_159_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_159_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_160_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_160_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_160_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_160_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_160_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_160_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_160_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_160_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_160_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_160_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_160_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_160_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_160_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_160_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_160_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_160_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_160_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_160_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_161_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_161_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_161_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_161_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_161_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_161_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_161_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_161_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_161_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_161_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_161_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_161_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_161_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_161_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_161_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_161_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_161_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_161_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_162_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_162_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_162_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_162_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_162_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_162_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_162_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_162_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_162_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_162_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_162_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_162_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_162_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_162_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_162_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_162_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_162_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_162_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_163_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_163_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_163_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_163_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_163_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_163_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_163_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_163_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_163_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_163_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_163_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_163_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_163_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_163_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_163_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_163_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_163_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_163_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_164_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_164_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_164_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_164_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_164_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_164_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_164_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_164_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_164_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_164_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_164_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_164_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_164_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_164_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_164_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_164_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_164_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_164_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_165_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_165_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_165_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_165_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_165_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_165_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_165_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_165_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_165_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_165_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_165_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_165_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_165_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_165_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_165_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_165_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_165_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_165_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_166_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_166_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_166_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_166_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_166_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_166_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_166_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_166_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_166_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_166_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_166_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_166_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_166_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_166_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_166_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_166_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_166_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_166_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_167_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_167_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_167_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_167_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_167_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_167_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_167_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_167_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_167_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_167_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_167_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_167_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_167_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_167_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_167_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_167_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_167_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_167_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_168_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_168_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_168_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_168_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_168_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_168_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_168_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_168_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_168_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_168_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_168_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_168_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_168_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_168_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_168_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_168_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_168_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_168_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_169_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_169_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_169_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_169_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_169_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_169_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_169_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_169_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_169_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_169_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_169_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_169_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_169_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_169_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_169_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_169_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_169_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_169_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_170_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_170_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_170_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_170_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_170_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_170_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_170_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_170_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_170_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_170_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_170_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_170_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_170_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_170_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_170_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_170_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_170_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_170_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_171_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_171_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_171_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_171_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_171_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_171_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_171_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_171_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_171_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_171_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_171_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_171_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_171_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_171_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_171_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_171_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_171_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_171_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_172_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_172_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_172_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_172_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_172_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_172_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_172_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_172_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_172_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_172_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_172_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_172_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_172_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_172_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_172_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_172_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_172_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_172_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_173_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_173_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_173_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_173_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_173_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_173_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_173_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_173_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_173_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_173_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_173_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_173_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_173_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_173_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_173_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_173_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_173_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_173_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_174_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_174_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_174_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_174_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_174_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_174_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_174_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_174_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_174_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_174_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_174_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_174_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_174_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_174_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_174_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_174_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_174_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_174_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_175_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_175_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_175_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_175_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_175_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_175_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_175_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_175_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_175_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_175_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_175_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_175_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_175_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_175_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_175_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_175_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_175_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_175_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_176_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_176_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_176_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_176_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_176_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_176_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_176_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_176_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_176_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_176_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_176_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_176_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_176_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_176_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_176_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_176_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_176_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_176_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_177_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_177_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_177_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_177_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_177_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_177_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_177_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_177_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_177_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_177_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_177_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_177_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_177_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_177_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_177_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_177_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_177_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_177_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_178_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_178_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_178_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_178_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_178_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_178_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_178_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_178_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_178_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_178_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_178_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_178_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_178_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_178_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_178_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_178_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_178_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_178_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_179_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_179_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_179_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_179_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_179_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_179_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_179_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_179_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_179_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_179_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_179_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_179_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_179_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_179_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_179_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_179_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_179_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_179_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_180_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_180_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_180_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_180_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_180_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_180_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_180_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_180_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_180_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_180_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_180_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_180_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_180_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_180_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_180_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_180_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_180_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_180_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_181_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_181_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_181_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_181_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_181_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_181_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_181_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_181_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_181_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_181_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_181_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_181_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_181_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_181_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_181_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_181_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_181_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_181_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_182_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_182_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_182_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_182_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_182_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_182_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_182_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_182_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_182_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_182_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_182_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_182_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_182_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_182_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_182_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_182_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_182_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_182_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_183_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_183_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_183_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_183_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_183_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_183_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_183_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_183_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_183_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_183_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_183_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_183_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_183_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_183_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_183_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_183_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_183_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_183_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_184_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_184_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_184_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_184_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_184_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_184_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_184_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_184_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_184_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_184_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_184_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_184_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_184_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_184_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_184_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_184_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_184_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_184_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_185_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_185_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_185_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_185_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_185_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_185_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_185_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_185_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_185_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_185_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_185_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_185_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_185_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_185_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_185_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_185_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_185_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_185_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_186_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_186_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_186_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_186_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_186_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_186_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_186_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_186_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_186_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_186_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_186_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_186_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_186_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_186_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_186_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_186_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_186_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_186_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_187_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_187_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_187_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_187_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_187_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_187_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_187_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_187_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_187_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_187_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_187_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_187_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_187_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_187_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_187_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_187_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_187_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_187_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_188_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_188_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_188_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_188_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_188_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_188_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_188_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_188_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_188_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_188_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_188_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_188_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_188_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_188_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_188_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_188_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_188_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_188_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_189_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_189_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_189_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_189_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_189_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_189_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_189_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_189_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_189_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_189_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_189_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_189_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_189_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_189_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_189_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_189_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_189_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_189_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_190_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_190_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_190_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_190_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_190_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_190_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_190_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_190_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_190_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_190_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_190_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_190_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_190_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_190_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_190_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_190_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_190_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_190_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_191_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_191_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_191_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_191_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_191_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_191_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_191_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_191_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_191_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_191_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_191_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_191_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_191_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_191_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_191_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_191_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_191_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_191_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_192_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_192_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_192_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_192_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_192_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_192_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_192_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_192_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_192_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_192_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_192_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_192_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_192_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_192_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_192_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_192_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_192_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_192_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_193_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_193_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_193_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_193_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_193_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_193_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_193_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_193_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_193_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_193_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_193_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_193_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_193_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_193_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_193_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_193_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_193_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_193_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_194_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_194_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_194_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_194_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_194_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_194_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_194_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_194_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_194_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_194_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_194_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_194_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_194_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_194_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_194_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_194_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_194_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_194_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_195_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_195_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_195_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_195_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_195_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_195_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_195_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_195_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_195_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_195_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_195_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_195_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_195_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_195_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_195_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_195_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_195_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_195_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_196_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_196_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_196_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_196_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_196_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_196_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_196_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_196_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_196_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_196_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_196_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_196_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_196_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_196_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_196_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_196_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_196_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_196_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_197_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_197_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_197_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_197_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_197_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_197_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_197_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_197_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_197_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_197_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_197_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_197_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_197_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_197_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_197_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_197_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_197_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_197_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_198_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_198_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_198_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_198_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_198_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_198_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_198_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_198_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_198_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_198_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_198_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_198_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_198_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_198_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_198_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_198_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_198_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_198_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_199_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_199_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_199_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_199_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_199_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_199_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_199_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_199_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_199_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_199_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_199_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_199_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_199_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_199_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_199_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_199_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_199_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_199_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_200_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_200_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_200_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_200_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_200_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_200_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_200_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_200_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_200_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_200_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_200_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_200_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_200_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_200_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_200_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_200_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_200_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_200_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_201_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_201_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_201_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_201_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_201_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_201_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_201_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_201_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_201_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_201_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_201_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_201_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_201_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_201_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_201_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_201_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_201_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_201_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_202_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_202_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_202_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_202_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_202_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_202_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_202_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_202_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_202_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_202_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_202_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_202_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_202_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_202_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_202_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_202_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_202_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_202_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_203_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_203_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_203_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_203_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_203_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_203_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_203_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_203_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_203_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_203_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_203_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_203_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_203_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_203_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_203_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_203_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_203_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_203_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_204_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_204_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_204_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_204_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_204_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_204_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_204_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_204_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_204_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_204_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_204_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_204_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_204_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_204_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_204_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_204_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_204_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_204_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_205_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_205_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_205_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_205_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_205_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_205_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_205_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_205_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_205_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_205_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_205_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_205_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_205_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_205_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_205_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_205_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_205_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_205_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_206_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_206_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_206_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_206_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_206_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_206_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_206_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_206_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_206_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_206_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_206_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_206_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_206_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_206_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_206_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_206_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_206_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_206_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_207_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_207_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_207_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_207_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_207_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_207_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_207_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_207_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_207_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_207_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_207_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_207_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_207_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_207_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_207_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_207_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_207_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_207_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_208_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_208_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_208_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_208_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_208_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_208_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_208_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_208_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_208_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_208_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_208_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_208_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_208_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_208_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_208_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_208_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_208_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_208_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_209_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_209_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_209_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_209_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_209_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_209_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_209_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_209_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_209_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_209_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_209_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_209_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_209_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_209_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_209_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_209_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_209_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_209_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_210_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_210_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_210_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_210_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_210_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_210_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_210_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_210_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_210_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_210_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_210_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_210_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_210_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_210_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_210_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_210_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_210_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_210_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_211_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_211_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_211_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_211_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_211_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_211_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_211_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_211_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_211_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_211_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_211_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_211_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_211_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_211_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_211_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_211_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_211_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_211_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_212_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_212_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_212_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_212_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_212_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_212_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_212_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_212_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_212_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_212_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_212_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_212_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_212_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_212_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_212_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_212_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_212_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_212_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_213_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_213_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_213_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_213_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_213_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_213_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_213_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_213_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_213_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_213_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_213_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_213_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_213_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_213_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_213_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_213_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_213_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_213_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_214_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_214_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_214_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_214_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_214_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_214_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_214_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_214_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_214_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_214_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_214_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_214_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_214_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_214_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_214_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_214_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_214_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_214_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_215_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_215_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_215_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_215_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_215_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_215_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_215_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_215_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_215_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_215_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_215_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_215_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_215_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_215_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_215_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_215_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_215_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_215_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_216_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_216_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_216_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_216_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_216_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_216_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_216_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_216_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_216_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_216_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_216_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_216_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_216_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_216_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_216_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_216_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_216_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_216_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_217_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_217_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_217_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_217_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_217_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_217_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_217_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_217_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_217_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_217_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_217_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_217_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_217_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_217_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_217_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_217_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_217_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_217_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_218_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_218_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_218_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_218_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_218_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_218_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_218_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_218_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_218_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_218_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_218_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_218_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_218_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_218_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_218_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_218_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_218_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_218_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_219_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_219_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_219_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_219_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_219_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_219_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_219_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_219_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_219_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_219_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_219_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_219_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_219_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_219_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_219_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_219_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_219_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_219_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_220_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_220_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_220_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_220_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_220_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_220_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_220_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_220_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_220_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_220_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_220_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_220_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_220_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_220_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_220_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_220_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_220_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_220_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_221_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_221_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_221_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_221_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_221_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_221_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_221_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_221_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_221_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_221_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_221_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_221_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_221_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_221_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_221_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_221_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_221_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_221_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_222_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_222_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_222_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_222_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_222_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_222_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_222_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_222_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_222_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_222_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_222_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_222_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_222_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_222_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_222_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_222_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_222_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_222_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_223_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_223_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_223_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_223_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_223_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_223_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_223_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_223_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_223_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_223_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_223_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_223_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_223_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_223_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_223_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_223_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_223_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_223_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_224_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_224_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_224_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_224_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_224_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_224_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_224_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_224_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_224_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_224_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_224_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_224_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_224_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_224_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_224_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_224_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_224_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_224_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_225_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_225_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_225_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_225_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_225_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_225_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_225_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_225_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_225_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_225_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_225_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_225_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_225_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_225_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_225_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_225_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_225_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_225_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_226_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_226_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_226_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_226_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_226_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_226_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_226_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_226_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_226_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_226_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_226_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_226_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_226_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_226_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_226_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_226_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_226_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_226_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_227_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_227_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_227_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_227_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_227_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_227_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_227_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_227_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_227_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_227_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_227_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_227_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_227_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_227_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_227_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_227_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_227_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_227_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_228_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_228_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_228_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_228_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_228_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_228_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_228_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_228_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_228_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_228_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_228_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_228_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_228_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_228_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_228_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_228_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_228_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_228_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_229_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_229_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_229_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_229_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_229_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_229_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_229_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_229_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_229_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_229_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_229_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_229_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_229_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_229_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_229_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_229_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_229_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_229_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_230_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_230_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_230_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_230_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_230_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_230_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_230_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_230_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_230_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_230_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_230_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_230_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_230_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_230_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_230_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_230_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_230_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_230_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_231_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_231_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_231_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_231_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_231_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_231_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_231_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_231_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_231_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_231_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_231_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_231_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_231_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_231_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_231_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_231_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_231_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_231_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_232_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_232_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_232_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_232_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_232_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_232_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_232_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_232_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_232_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_232_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_232_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_232_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_232_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_232_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_232_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_232_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_232_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_232_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_233_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_233_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_233_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_233_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_233_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_233_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_233_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_233_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_233_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_233_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_233_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_233_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_233_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_233_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_233_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_233_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_233_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_233_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_234_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_234_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_234_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_234_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_234_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_234_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_234_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_234_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_234_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_234_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_234_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_234_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_234_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_234_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_234_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_234_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_234_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_234_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_235_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_235_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_235_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_235_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_235_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_235_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_235_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_235_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_235_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_235_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_235_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_235_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_235_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_235_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_235_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_235_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_235_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_235_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_236_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_236_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_236_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_236_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_236_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_236_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_236_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_236_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_236_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_236_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_236_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_236_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_236_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_236_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_236_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_236_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_236_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_236_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_237_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_237_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_237_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_237_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_237_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_237_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_237_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_237_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_237_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_237_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_237_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_237_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_237_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_237_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_237_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_237_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_237_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_237_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_238_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_238_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_238_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_238_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_238_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_238_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_238_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_238_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_238_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_238_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_238_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_238_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_238_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_238_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_238_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_238_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_238_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_238_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_239_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_239_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_239_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_239_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_239_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_239_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_239_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_239_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_239_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_239_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_239_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_239_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_239_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_239_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_239_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_239_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_239_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_239_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_240_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_240_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_240_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_240_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_240_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_240_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_240_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_240_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_240_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_240_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_240_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_240_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_240_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_240_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_240_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_240_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_240_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_240_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_241_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_241_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_241_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_241_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_241_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_241_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_241_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_241_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_241_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_241_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_241_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_241_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_241_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_241_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_241_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_241_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_241_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_241_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_242_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_242_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_242_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_242_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_242_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_242_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_242_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_242_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_242_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_242_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_242_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_242_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_242_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_242_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_242_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_242_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_242_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_242_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_243_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_243_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_243_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_243_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_243_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_243_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_243_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_243_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_243_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_243_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_243_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_243_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_243_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_243_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_243_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_243_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_243_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_243_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_244_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_244_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_244_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_244_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_244_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_244_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_244_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_244_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_244_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_244_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_244_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_244_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_244_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_244_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_244_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_244_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_244_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_244_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_245_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_245_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_245_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_245_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_245_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_245_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_245_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_245_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_245_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_245_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_245_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_245_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_245_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_245_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_245_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_245_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_245_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_245_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_246_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_246_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_246_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_246_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_246_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_246_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_246_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_246_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_246_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_246_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_246_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_246_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_246_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_246_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_246_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_246_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_246_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_246_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_247_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_247_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_247_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_247_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_247_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_247_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_247_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_247_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_247_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_247_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_247_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_247_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_247_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_247_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_247_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_247_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_247_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_247_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_248_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_248_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_248_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_248_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_248_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_248_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_248_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_248_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_248_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_248_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_248_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_248_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_248_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_248_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_248_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_248_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_248_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_248_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_249_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_249_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_249_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_249_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_249_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_249_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_249_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_249_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_249_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_249_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_249_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_249_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_249_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_249_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_249_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_249_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_249_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_249_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_250_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_250_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_250_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_250_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_250_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_250_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_250_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_250_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_250_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_250_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_250_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_250_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_250_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_250_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_250_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_250_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_250_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_250_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_251_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_251_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_251_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_251_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_251_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_251_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_251_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_251_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_251_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_251_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_251_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_251_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_251_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_251_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_251_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_251_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_251_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_251_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_252_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_252_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_252_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_252_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_252_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_252_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_252_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_252_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_252_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_252_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_252_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_252_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_252_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_252_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_252_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_252_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_252_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_252_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_256_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_256_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_256_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_256_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_256_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_256_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_256_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_256_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_256_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_257_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_257_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_257_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_257_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_257_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_257_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_257_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_257_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_257_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_258_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_258_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_258_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_258_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_258_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_258_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_258_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_258_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_258_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_259_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_259_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_259_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_259_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_259_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_259_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_259_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_259_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_259_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_260_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_260_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_260_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_260_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_260_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_260_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_260_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_260_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_260_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_261_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_261_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_261_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_261_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_261_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_261_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_261_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_261_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_261_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_262_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_262_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_262_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_262_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_262_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_262_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_262_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_262_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_262_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_263_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_263_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_263_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_263_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_263_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_263_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_263_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_263_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_263_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_264_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_264_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_264_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_264_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_264_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_264_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_264_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_264_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_264_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_265_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_265_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_265_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_265_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
#define LPD_XPPU_CFG_APERPERM_309_PARITY_SHIFT 28
#define LPD_XPPU_CFG_APERPERM_309_PARITY_MASK 0xF0000000U
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_310_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_310_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_310_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_310_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_310_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_310_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_310_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_310_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_310_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_310_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_310_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_310_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_310_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_310_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_310_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_310_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_310_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_310_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_311_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_311_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_311_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_311_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_311_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_311_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_311_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_311_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_311_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_311_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_311_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_311_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_311_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_311_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_311_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_311_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_311_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_311_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_312_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_312_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_312_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_312_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_312_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_312_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_312_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_312_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_312_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_312_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_312_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_312_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_312_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_312_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_312_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_312_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_312_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_312_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_313_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_313_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_313_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_313_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_313_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_313_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_313_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_313_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_313_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_313_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_313_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_313_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_313_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_313_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_313_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_313_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_313_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_313_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_314_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_314_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_314_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_314_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_314_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_314_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_314_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_314_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_314_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_314_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_314_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_314_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_314_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_314_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_314_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_314_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_314_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_314_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_315_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_315_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_315_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_315_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_315_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_315_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_315_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_315_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_315_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_315_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_315_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_315_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_315_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_315_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_315_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_315_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_315_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_315_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_316_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_316_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_316_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_316_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_316_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_316_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_316_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_316_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_316_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_316_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_316_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_316_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_316_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_316_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_316_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_316_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_316_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_316_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_317_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_317_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_317_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_317_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_317_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_317_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_317_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_317_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_317_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_317_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_317_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_317_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_317_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_317_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_317_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_317_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_317_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_317_PARITY_MASK 0xF0000000U
-
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
#undef LPD_XPPU_CFG_APERPERM_318_PERMISSION_DEFVAL
#define LPD_XPPU_CFG_APERPERM_325_PARITY_SHIFT 28
#define LPD_XPPU_CFG_APERPERM_325_PARITY_MASK 0xF0000000U
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_326_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_326_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_326_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_326_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_326_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_326_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_326_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_326_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_326_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_326_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_326_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_326_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_326_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_326_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_326_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_326_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_326_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_326_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_327_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_327_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_327_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_327_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_327_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_327_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_327_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_327_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_327_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_327_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_327_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_327_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_327_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_327_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_327_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_327_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_327_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_327_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_328_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_328_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_328_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_328_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_328_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_328_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_328_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_328_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_328_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_328_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_328_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_328_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_328_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_328_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_328_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_328_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_328_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_328_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_329_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_329_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_329_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_329_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_329_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_329_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_329_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_329_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_329_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_329_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_329_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_329_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_329_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_329_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_329_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_329_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_329_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_329_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_330_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_330_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_330_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_330_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_330_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_330_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_330_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_330_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_330_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_330_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_330_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_330_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_330_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_330_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_330_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_330_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_330_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_330_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_331_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_331_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_331_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_331_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_331_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_331_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_331_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_331_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_331_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_331_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_331_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_331_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_331_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_331_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_331_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_331_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_331_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_331_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_332_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_332_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_332_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_332_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_332_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_332_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_332_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_332_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_332_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_332_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_332_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_332_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_332_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_332_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_332_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_332_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_332_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_332_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_333_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_333_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_333_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_333_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_333_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_333_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_333_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_333_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_333_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_333_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_333_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_333_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_333_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_333_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_333_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_333_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_333_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_333_PARITY_MASK 0xF0000000U
-
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
#undef LPD_XPPU_CFG_APERPERM_334_PERMISSION_DEFVAL
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_341_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_341_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_341_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_341_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_341_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_342_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_342_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_342_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_342_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_342_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_342_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_342_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_342_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_342_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_342_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_342_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_342_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_342_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_342_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_342_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_342_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_342_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_342_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_343_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_343_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_343_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_343_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_343_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_343_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_343_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_343_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_343_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_343_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_343_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_343_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_343_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_343_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_343_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_343_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_343_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_343_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_344_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_344_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_344_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_344_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_344_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_344_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_344_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_344_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_344_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_344_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_344_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_344_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_344_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_344_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_344_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_344_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_344_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_344_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_345_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_345_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_345_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_345_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_345_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_345_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_345_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_345_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_345_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_345_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_345_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_345_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_345_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_345_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_345_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_345_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_345_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_345_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_346_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_346_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_346_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_346_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_346_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_346_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_346_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_346_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_346_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_346_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_346_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_346_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_346_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_346_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_346_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_346_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_346_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_346_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_347_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_347_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_347_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_347_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_347_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_347_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_347_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_347_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_347_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_347_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_347_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_347_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_347_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_347_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_347_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_347_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_347_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_347_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_348_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_348_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_348_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_348_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_348_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_348_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_348_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_348_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_348_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_348_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_348_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_348_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_348_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_348_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_348_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_348_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_348_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_348_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_349_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_349_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_349_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_349_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_349_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_349_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_341_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_341_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_341_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_349_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_349_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_349_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_349_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_349_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_349_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_341_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_349_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_349_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_349_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_349_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_349_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_349_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_341_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_341_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_341_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_341_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_341_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
#define LPD_XPPU_CFG_APERPERM_357_PARITY_SHIFT 28
#define LPD_XPPU_CFG_APERPERM_357_PARITY_MASK 0xF0000000U
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_358_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_358_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_358_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_358_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_358_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_358_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_358_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_358_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_358_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_358_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_358_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_358_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_358_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_358_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_358_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_358_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_358_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_358_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_359_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_359_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_359_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_359_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_359_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_359_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_359_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_359_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_359_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_359_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_359_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_359_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_359_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_359_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_359_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_359_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_359_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_359_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_360_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_360_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_360_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_360_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_360_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_360_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_360_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_360_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_360_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_360_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_360_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_360_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_360_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_360_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_360_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_360_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_360_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_360_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_361_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_361_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_361_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_361_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_361_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_361_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_361_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_361_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_361_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_361_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_361_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_361_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_361_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_361_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_361_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_361_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_361_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_361_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_362_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_362_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_362_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_362_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_362_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_362_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_362_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_362_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_362_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_362_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_362_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_362_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_362_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_362_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_362_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_362_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_362_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_362_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_363_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_363_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_363_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_363_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_363_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_363_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_363_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_363_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_363_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_363_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_363_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_363_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_363_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_363_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_363_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_363_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_363_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_363_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_364_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_364_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_364_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_364_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_364_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_364_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_364_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_364_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_364_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_364_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_364_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_364_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_364_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_364_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_364_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_364_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_364_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_364_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_365_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_365_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_365_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_365_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_365_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_365_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_365_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_365_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_365_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_365_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_365_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_365_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_365_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_365_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_365_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_365_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_365_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_365_PARITY_MASK 0xF0000000U
-
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
#undef LPD_XPPU_CFG_APERPERM_366_PERMISSION_DEFVAL
#undef LPD_XPPU_CFG_APERPERM_381_PARITY_SHIFT
#undef LPD_XPPU_CFG_APERPERM_381_PARITY_MASK
#define LPD_XPPU_CFG_APERPERM_381_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_381_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_381_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_382_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_382_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_382_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_382_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_382_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_383_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_383_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_383_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_383_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_383_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_384_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_384_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_384_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_384_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_384_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_384_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_384_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_384_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_384_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_384_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_384_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_384_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_384_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_384_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_384_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_384_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_384_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_384_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_385_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_385_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_385_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_385_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_385_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_385_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_385_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_385_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_385_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_385_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_385_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_385_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_385_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_385_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_385_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_385_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_385_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_385_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_386_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_386_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_386_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_386_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_386_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_386_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_386_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_386_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_386_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_386_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_386_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_386_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_386_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_386_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_386_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_386_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_386_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_386_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_387_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_387_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_387_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_387_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_387_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_387_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_387_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_387_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_387_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_387_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_387_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_387_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_387_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_387_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_387_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_387_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_387_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_387_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_388_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_388_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_388_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_388_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_388_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_388_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_388_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_388_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_388_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_388_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_388_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_388_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_388_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_388_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_388_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_388_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_388_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_388_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_389_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_389_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_389_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_389_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_389_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_389_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_389_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_389_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_389_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_389_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_389_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_389_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_389_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_389_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_389_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_389_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_389_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_389_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_390_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_390_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_390_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_390_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_390_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_390_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_390_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_390_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_390_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_390_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_390_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_390_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_390_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_390_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_390_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_390_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_390_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_390_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_391_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_391_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_391_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_391_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_391_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_391_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_391_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_391_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_391_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_391_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_391_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_391_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_391_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_391_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_391_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_391_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_391_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_391_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_392_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_392_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_392_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_392_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_392_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_392_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_392_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_392_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_392_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_392_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_392_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_392_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_392_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_392_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_392_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_392_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_392_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_392_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_393_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_393_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_393_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_393_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_393_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_393_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_393_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_393_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_393_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_393_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_393_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_393_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_393_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_393_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_393_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_393_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_393_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_393_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_394_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_394_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_394_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_394_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_394_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_394_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_394_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_394_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_394_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_394_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_394_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_394_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_394_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_394_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_394_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_394_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_394_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_394_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_395_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_395_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_395_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_395_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_395_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_395_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_395_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_395_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_395_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_395_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_395_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_395_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_395_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_395_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_395_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_395_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_395_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_395_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_396_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_396_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_396_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_396_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_396_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_396_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_396_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_396_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_396_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_396_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_396_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_396_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_396_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_396_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_396_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_396_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_396_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_396_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_397_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_397_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_397_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_397_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_397_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_397_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_397_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_397_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_397_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_397_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_397_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_397_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_397_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_397_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_397_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_397_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_397_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_397_PARITY_MASK 0xF0000000U
-
-/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
- h.*/
-#undef LPD_XPPU_CFG_APERPERM_398_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_398_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_398_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_398_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_398_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_398_PERMISSION_MASK 0x000FFFFFU
-
-/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_398_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_398_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_398_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_398_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_398_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_398_TRUSTZONE_MASK 0x08000000U
-
-/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
- bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_398_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_398_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_398_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_398_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_398_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_398_PARITY_MASK 0xF0000000U
+#define LPD_XPPU_CFG_APERPERM_381_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_381_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_399_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_399_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_399_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_399_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_399_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_399_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_382_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_382_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_382_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_399_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_399_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_399_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_399_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_399_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_399_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_382_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_399_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_399_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_399_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_399_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_399_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_399_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_382_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_382_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_382_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_382_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_382_PARITY_MASK 0xF0000000U
/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
h.*/
-#undef LPD_XPPU_CFG_APERPERM_400_PERMISSION_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_400_PERMISSION_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_400_PERMISSION_MASK
-#define LPD_XPPU_CFG_APERPERM_400_PERMISSION_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_400_PERMISSION_SHIFT 0
-#define LPD_XPPU_CFG_APERPERM_400_PERMISSION_MASK 0x000FFFFFU
+#undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_383_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_383_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_383_PERMISSION_MASK 0x000FFFFFU
/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
-#undef LPD_XPPU_CFG_APERPERM_400_TRUSTZONE_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_400_TRUSTZONE_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_400_TRUSTZONE_MASK
-#define LPD_XPPU_CFG_APERPERM_400_TRUSTZONE_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_400_TRUSTZONE_SHIFT 27
-#define LPD_XPPU_CFG_APERPERM_400_TRUSTZONE_MASK 0x08000000U
+#undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_383_TRUSTZONE_MASK 0x08000000U
/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
-#undef LPD_XPPU_CFG_APERPERM_400_PARITY_DEFVAL
-#undef LPD_XPPU_CFG_APERPERM_400_PARITY_SHIFT
-#undef LPD_XPPU_CFG_APERPERM_400_PARITY_MASK
-#define LPD_XPPU_CFG_APERPERM_400_PARITY_DEFVAL 0x00000000
-#define LPD_XPPU_CFG_APERPERM_400_PARITY_SHIFT 28
-#define LPD_XPPU_CFG_APERPERM_400_PARITY_MASK 0xF0000000U
+#undef LPD_XPPU_CFG_APERPERM_383_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_383_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_383_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_383_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_383_PARITY_MASK 0xF0000000U
+
+/*Whether an APB access to the "hole" region and to an unimplemented register space causes PSLVERR*/
+#undef LPD_XPPU_SINK_ERR_CTRL_PSLVERR_DEFVAL
+#undef LPD_XPPU_SINK_ERR_CTRL_PSLVERR_SHIFT
+#undef LPD_XPPU_SINK_ERR_CTRL_PSLVERR_MASK
+#define LPD_XPPU_SINK_ERR_CTRL_PSLVERR_DEFVAL 0x00000000
+#define LPD_XPPU_SINK_ERR_CTRL_PSLVERR_SHIFT 0
+#define LPD_XPPU_SINK_ERR_CTRL_PSLVERR_MASK 0x00000001U
/*0=Bypass XPPU (transparent) 1=Enable XPPU permission checking*/
#undef LPD_XPPU_CFG_CTRL_ENABLE_DEFVAL
#define LPD_XPPU_CFG_CTRL_ENABLE_DEFVAL 0x00000000
#define LPD_XPPU_CFG_CTRL_ENABLE_SHIFT 0
#define LPD_XPPU_CFG_CTRL_ENABLE_MASK 0x00000001U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK
+#define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT 7
+#define LPD_XPPU_CFG_IEN_APER_PARITY_MASK 0x00000080U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_TZ_MASK
+#define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT 6
+#define LPD_XPPU_CFG_IEN_APER_TZ_MASK 0x00000040U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL
+#undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT
+#undef LPD_XPPU_CFG_IEN_APER_PERM_MASK
+#define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT 5
+#define LPD_XPPU_CFG_IEN_APER_PERM_MASK 0x00000020U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK
+#define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT 3
+#define LPD_XPPU_CFG_IEN_MID_PARITY_MASK 0x00000008U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_RO_MASK
+#define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_RO_SHIFT 2
+#define LPD_XPPU_CFG_IEN_MID_RO_MASK 0x00000004U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL
+#undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT
+#undef LPD_XPPU_CFG_IEN_MID_MISS_MASK
+#define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT 1
+#define LPD_XPPU_CFG_IEN_MID_MISS_MASK 0x00000002U
+
+/*See Interuppt Status Register for details*/
+#undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL
+#undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT
+#undef LPD_XPPU_CFG_IEN_INV_APB_MASK
+#define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_IEN_INV_APB_SHIFT 0
+#define LPD_XPPU_CFG_IEN_INV_APB_MASK 0x00000001U
+#undef LPD_XPPU_CFG_APERPERM_152_OFFSET
+#define LPD_XPPU_CFG_APERPERM_152_OFFSET 0XFF981260
+
+/*This field defines the MASTER ID match criteria. Each entry in the IDL corresponds to a bit in this field. 0=not match, 1=mat
+ h.*/
+#undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK
+#define LPD_XPPU_CFG_APERPERM_152_PERMISSION_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_152_PERMISSION_SHIFT 0
+#define LPD_XPPU_CFG_APERPERM_152_PERMISSION_MASK 0x000FFFFFU
+
+/*1=secure or non-secure transactions are allowed 0=only secure transactiona are allowed*/
+#undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK
+#define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_SHIFT 27
+#define LPD_XPPU_CFG_APERPERM_152_TRUSTZONE_MASK 0x08000000U
+
+/*SW must calculate and set up parity, if parity check is enabled by the CTRL register. 31: parity for bits 19:15 30: parity fo
+ bits 14:10 29: parity for bits 9:5 28: parity for bits 27, 4:0*/
+#undef LPD_XPPU_CFG_APERPERM_152_PARITY_DEFVAL
+#undef LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT
+#undef LPD_XPPU_CFG_APERPERM_152_PARITY_MASK
+#define LPD_XPPU_CFG_APERPERM_152_PARITY_DEFVAL 0x00000000
+#define LPD_XPPU_CFG_APERPERM_152_PARITY_SHIFT 28
+#define LPD_XPPU_CFG_APERPERM_152_PARITY_MASK 0xF0000000U
#undef SERDES_PLL_REF_SEL0_OFFSET
#define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000
#undef SERDES_PLL_REF_SEL1_OFFSET
#define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 0XFD40E368
#undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET
#define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40E36C
+#undef SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET
+#define SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET 0XFD402368
+#undef SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET
+#define SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40236C
#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET
#define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 0XFD406368
#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET
#define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 0XFD40636C
+#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET
+#define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD402370
+#undef SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET
+#define SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET 0XFD402374
+#undef SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET
+#define SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET 0XFD402378
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET 0XFD40237C
#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET
#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 0XFD406370
#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET
#define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4
#undef SERDES_L3_TXPMA_ST_0_OFFSET
#define SERDES_L3_TXPMA_ST_0_OFFSET 0XFD40CB00
-#undef SERDES_L0_TM_AUX_0_OFFSET
-#define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC
#undef SERDES_L2_TM_AUX_0_OFFSET
#define SERDES_L2_TM_AUX_0_OFFSET 0XFD4090CC
#undef SERDES_L0_TM_DIG_8_OFFSET
#define SERDES_L2_TM_DIG_8_OFFSET 0XFD409074
#undef SERDES_L3_TM_DIG_8_OFFSET
#define SERDES_L3_TM_DIG_8_OFFSET 0XFD40D074
-#undef SERDES_L0_TM_MISC2_OFFSET
-#define SERDES_L0_TM_MISC2_OFFSET 0XFD40189C
-#undef SERDES_L0_TM_IQ_ILL1_OFFSET
-#define SERDES_L0_TM_IQ_ILL1_OFFSET 0XFD4018F8
-#undef SERDES_L0_TM_IQ_ILL2_OFFSET
-#define SERDES_L0_TM_IQ_ILL2_OFFSET 0XFD4018FC
-#undef SERDES_L0_TM_ILL12_OFFSET
-#define SERDES_L0_TM_ILL12_OFFSET 0XFD401990
-#undef SERDES_L0_TM_E_ILL1_OFFSET
-#define SERDES_L0_TM_E_ILL1_OFFSET 0XFD401924
-#undef SERDES_L0_TM_E_ILL2_OFFSET
-#define SERDES_L0_TM_E_ILL2_OFFSET 0XFD401928
-#undef SERDES_L0_TM_IQ_ILL3_OFFSET
-#define SERDES_L0_TM_IQ_ILL3_OFFSET 0XFD401900
-#undef SERDES_L0_TM_E_ILL3_OFFSET
-#define SERDES_L0_TM_E_ILL3_OFFSET 0XFD40192C
-#undef SERDES_L0_TM_ILL8_OFFSET
-#define SERDES_L0_TM_ILL8_OFFSET 0XFD401980
-#undef SERDES_L0_TM_IQ_ILL8_OFFSET
-#define SERDES_L0_TM_IQ_ILL8_OFFSET 0XFD401914
-#undef SERDES_L0_TM_IQ_ILL9_OFFSET
-#define SERDES_L0_TM_IQ_ILL9_OFFSET 0XFD401918
-#undef SERDES_L0_TM_E_ILL8_OFFSET
-#define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940
-#undef SERDES_L0_TM_E_ILL9_OFFSET
-#define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944
#undef SERDES_L2_TM_MISC2_OFFSET
#define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C
#undef SERDES_L2_TM_IQ_ILL1_OFFSET
#define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940
#undef SERDES_L3_TM_E_ILL9_OFFSET
#define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944
-#undef SERDES_ICM_CFG0_OFFSET
-#define SERDES_ICM_CFG0_OFFSET 0XFD410010
-#undef SERDES_ICM_CFG1_OFFSET
-#define SERDES_ICM_CFG1_OFFSET 0XFD410014
-#undef SERDES_L1_TXPMD_TM_45_OFFSET
-#define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4
-#undef SERDES_L1_TX_ANA_TM_118_OFFSET
-#define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8
-#undef SERDES_L3_TX_ANA_TM_118_OFFSET
-#define SERDES_L3_TX_ANA_TM_118_OFFSET 0XFD40C1D8
-#undef SERDES_L3_TM_CDR5_OFFSET
-#define SERDES_L3_TM_CDR5_OFFSET 0XFD40DC14
-#undef SERDES_L3_TM_CDR16_OFFSET
-#define SERDES_L3_TM_CDR16_OFFSET 0XFD40DC40
-#undef SERDES_L3_TM_EQ0_OFFSET
-#define SERDES_L3_TM_EQ0_OFFSET 0XFD40D94C
-#undef SERDES_L3_TM_EQ1_OFFSET
-#define SERDES_L3_TM_EQ1_OFFSET 0XFD40D950
-#undef SERDES_L1_TXPMD_TM_48_OFFSET
-#define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0
-#undef SERDES_L1_TX_ANA_TM_18_OFFSET
-#define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048
-#undef SERDES_L3_TX_ANA_TM_18_OFFSET
-#define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048
#undef SERDES_L0_TM_RST_DLY_OFFSET
#define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4
#undef SERDES_L0_TM_ANA_BYP_15_OFFSET
#define SERDES_L0_TM_ANA_BYP_15_OFFSET 0XFD401038
#undef SERDES_L0_TM_ANA_BYP_12_OFFSET
#define SERDES_L0_TM_ANA_BYP_12_OFFSET 0XFD40102C
-#undef SERDES_L0_TM_DIG_21_OFFSET
-#define SERDES_L0_TM_DIG_21_OFFSET 0XFD4010A8
-#undef SERDES_L0_TM_DIG_10_OFFSET
-#define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C
#undef SERDES_L1_TM_RST_DLY_OFFSET
#define SERDES_L1_TM_RST_DLY_OFFSET 0XFD4059A4
#undef SERDES_L1_TM_ANA_BYP_15_OFFSET
#define SERDES_L1_TM_ANA_BYP_15_OFFSET 0XFD405038
#undef SERDES_L1_TM_ANA_BYP_12_OFFSET
#define SERDES_L1_TM_ANA_BYP_12_OFFSET 0XFD40502C
-#undef SERDES_L1_TM_DIG_21_OFFSET
-#define SERDES_L1_TM_DIG_21_OFFSET 0XFD4050A8
-#undef SERDES_L1_TM_DIG_10_OFFSET
-#define SERDES_L1_TM_DIG_10_OFFSET 0XFD40507C
#undef SERDES_L2_TM_RST_DLY_OFFSET
#define SERDES_L2_TM_RST_DLY_OFFSET 0XFD4099A4
#undef SERDES_L2_TM_ANA_BYP_15_OFFSET
#define SERDES_L2_TM_ANA_BYP_15_OFFSET 0XFD409038
#undef SERDES_L2_TM_ANA_BYP_12_OFFSET
#define SERDES_L2_TM_ANA_BYP_12_OFFSET 0XFD40902C
-#undef SERDES_L2_TM_DIG_21_OFFSET
-#define SERDES_L2_TM_DIG_21_OFFSET 0XFD4090A8
-#undef SERDES_L2_TM_DIG_10_OFFSET
-#define SERDES_L2_TM_DIG_10_OFFSET 0XFD40907C
#undef SERDES_L3_TM_RST_DLY_OFFSET
#define SERDES_L3_TM_RST_DLY_OFFSET 0XFD40D9A4
#undef SERDES_L3_TM_ANA_BYP_15_OFFSET
#define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038
#undef SERDES_L3_TM_ANA_BYP_12_OFFSET
#define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C
-#undef SERDES_L3_TM_DIG_10_OFFSET
-#define SERDES_L3_TM_DIG_10_OFFSET 0XFD40D07C
+#undef SERDES_ICM_CFG0_OFFSET
+#define SERDES_ICM_CFG0_OFFSET 0XFD410010
+#undef SERDES_ICM_CFG1_OFFSET
+#define SERDES_ICM_CFG1_OFFSET 0XFD410014
+#undef SERDES_L0_TXPMD_TM_45_OFFSET
+#define SERDES_L0_TXPMD_TM_45_OFFSET 0XFD400CB4
+#undef SERDES_L1_TXPMD_TM_45_OFFSET
+#define SERDES_L1_TXPMD_TM_45_OFFSET 0XFD404CB4
+#undef SERDES_L0_TX_ANA_TM_118_OFFSET
+#define SERDES_L0_TX_ANA_TM_118_OFFSET 0XFD4001D8
+#undef SERDES_L1_TX_ANA_TM_118_OFFSET
+#define SERDES_L1_TX_ANA_TM_118_OFFSET 0XFD4041D8
+#undef SERDES_L3_TX_ANA_TM_118_OFFSET
+#define SERDES_L3_TX_ANA_TM_118_OFFSET 0XFD40C1D8
+#undef SERDES_L3_TM_CDR5_OFFSET
+#define SERDES_L3_TM_CDR5_OFFSET 0XFD40DC14
+#undef SERDES_L3_TM_CDR16_OFFSET
+#define SERDES_L3_TM_CDR16_OFFSET 0XFD40DC40
+#undef SERDES_L3_TM_EQ0_OFFSET
+#define SERDES_L3_TM_EQ0_OFFSET 0XFD40D94C
+#undef SERDES_L3_TM_EQ1_OFFSET
+#define SERDES_L3_TM_EQ1_OFFSET 0XFD40D950
+#undef SERDES_L1_TXPMD_TM_48_OFFSET
+#define SERDES_L1_TXPMD_TM_48_OFFSET 0XFD404CC0
+#undef SERDES_L0_TXPMD_TM_48_OFFSET
+#define SERDES_L0_TXPMD_TM_48_OFFSET 0XFD400CC0
+#undef SERDES_L1_TX_ANA_TM_18_OFFSET
+#define SERDES_L1_TX_ANA_TM_18_OFFSET 0XFD404048
+#undef SERDES_L0_TX_ANA_TM_18_OFFSET
+#define SERDES_L0_TX_ANA_TM_18_OFFSET 0XFD400048
+#undef SERDES_L3_TX_ANA_TM_18_OFFSET
+#define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048
/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7
#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U
+/*Bit 3 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_DEFVAL
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_DEFVAL 0x00000080
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT 3
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK 0x00000008U
+
/*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/
#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL
#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
+/*Spread Spectrum No of Steps [7:0]*/
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU
+
/*Spread Spectrum No of Steps [10:8]*/
#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
+/*Spread Spectrum No of Steps [7:0]*/
+#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
+#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
+#define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000
+#define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0
+#define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU
+
+/*Spread Spectrum No of Steps [10:8]*/
+#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
+#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
+#define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000
+#define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
+#define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
+
/*Spread Spectrum No of Steps [7:0]*/
#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0
#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U
+/*Step Size for Spread Spectrum [7:0]*/
+#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
+#define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000
+#define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0
+#define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU
+
+/*Step Size for Spread Spectrum [15:8]*/
+#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
+#define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000
+#define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0
+#define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU
+
+/*Step Size for Spread Spectrum [23:16]*/
+#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
+#define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000
+#define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0
+#define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU
+
+/*Step Size for Spread Spectrum [25:24]*/
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U
+
+/*Enable/Disable test mode force on SS step size*/
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U
+
+/*Enable/Disable test mode force on SS no of steps*/
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5
+#define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U
+
/*Step Size for Spread Spectrum [7:0]*/
#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 4
#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 0x000000F0U
-/*Spare- not used*/
-#undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL
-#undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT
-#undef SERDES_L0_TM_AUX_0_BIT_2_MASK
-#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000
-#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5
-#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U
-
/*Spare- not used*/
#undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL
#undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT
#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4
#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U
-/*ILL calib counts BYPASSED with calcode bits*/
-#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
-#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
-#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
-#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000
-#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7
-#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U
-
-/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
-#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
-#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
-#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
-#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000
-#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0
-#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU
-
-/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
-#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
-#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
-#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
-#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000
-#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0
-#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU
-
-/*G1A pll ctr bypass value*/
-#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
-#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
-#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
-#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000
-#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0
-#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU
-
-/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/
-#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
-#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
-#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
-#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000
-#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0
-#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU
-
-/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/
-#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
-#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
-#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
-#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000
-#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0
-#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU
-
-/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
-#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
-#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
-#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
-#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000
-#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0
-#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU
-
-/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/
-#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
-#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
-#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
-#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000
-#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0
-#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU
-
-/*ILL calibration code change wait time*/
-#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
-#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
-#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
-#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002
-#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0
-#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU
-
-/*IQ ILL polytrim bypass value*/
-#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
-#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
-#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
-#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000
-#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0
-#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU
-
-/*bypass IQ polytrim*/
-#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
-#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
-#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
-#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000
-#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
-#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
-
-/*E ILL polytrim bypass value*/
-#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
-#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
-#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
-#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
-#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
-#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
-
-/*bypass E polytrim*/
-#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
-#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
-#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
-#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
-#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
-#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
-
/*ILL calib counts BYPASSED with calcode bits*/
#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0
#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U
-/*E ILL polytrim bypass value*/
-#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
-#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
-#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
-#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
-#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
-#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
+/*E ILL polytrim bypass value*/
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0
+#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU
+
+/*bypass E polytrim*/
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
+#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
+
+/*Delay apb reset by specified amount*/
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0
+#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
+
+/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
+#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
-/*bypass E polytrim*/
-#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
-#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
-#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
-#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000
-#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0
-#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U
+/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
+#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
, 7 - Unused*/
#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4
#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U
+/*Enable/disable DP post2 path*/
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U
+
+/*Override enable/disable of DP post2 path*/
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U
+
+/*Override enable/disable of DP post1 path*/
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U
+
+/*Enable/disable DP main path*/
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U
+
+/*Override enable/disable of DP main path*/
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0
+#define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U
+
/*Enable/disable DP post2 path*/
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U
+/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
+#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
+#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
+#define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000
+#define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0
+#define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U
+
/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0
#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU
+/*Margining factor value*/
+#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
+#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
+#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK
+#define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000
+#define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0
+#define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU
+
/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
+/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
+#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
+#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
+#define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
+#define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
+#define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
+
/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002
#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0
#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU
-
-/*Delay apb reset by specified amount*/
-#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL
-#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
-#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK
-#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
-#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0
-#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
-
-/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
-#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
-#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
-#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
-#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
-#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
-#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
-
-/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
-#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
-#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
-#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
-
-/*Enable Bypass for <5> of TM_ANA_BYPS_12*/
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_DEFVAL
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK
-#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_DEFVAL 0x00000000
-#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT 4
-#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK 0x00000010U
-
-/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/
-#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL
-#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
-#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK
-#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000
-#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0
-#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U
-
-/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/
-#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL
-#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
-#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK
-#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000
-#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0
-#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U
-
-/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/
-#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
-#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
-#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
-#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
-#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
-#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
-
-/*Delay apb reset by specified amount*/
-#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL
-#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
-#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK
-#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
-#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0
-#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
-
-/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
-#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
-#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
-#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
-#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
-#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
-#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
-
-/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
-#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
-#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
-#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
-
-/*Enable Bypass for <5> of TM_ANA_BYPS_12*/
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_DEFVAL
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK
-#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_DEFVAL 0x00000000
-#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT 4
-#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK 0x00000010U
-
-/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/
-#undef SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL
-#undef SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
-#undef SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK
-#define SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000
-#define SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0
-#define SERDES_L1_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U
-
-/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/
-#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
-#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
-#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
-#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
-#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
-#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
-
-/*Delay apb reset by specified amount*/
-#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL
-#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
-#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK
-#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
-#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0
-#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
-
-/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
-#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
-#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
-#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
-#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
-#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
-#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
-
-/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
-#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
-#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
-#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
-
-/*Enable Bypass for <5> of TM_ANA_BYPS_12*/
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_DEFVAL
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK
-#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_DEFVAL 0x00000000
-#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT 4
-#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK 0x00000010U
-
-/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/
-#undef SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL
-#undef SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT
-#undef SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK
-#define SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000
-#define SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0
-#define SERDES_L2_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U
-
-/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/
-#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
-#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
-#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
-#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
-#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
-#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
-
-/*Delay apb reset by specified amount*/
-#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL
-#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
-#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK
-#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000
-#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0
-#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU
-
-/*Enable Bypass for <7> of TM_ANA_BYPS_15*/
-#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
-#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
-#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
-#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000
-#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6
-#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U
-
-/*Enable Bypass for <7> of TM_ANA_BYPS_12*/
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
-#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000
-#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6
-#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U
-
-/*Enable Bypass for <5> of TM_ANA_BYPS_12*/
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_DEFVAL
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK
-#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_DEFVAL 0x00000000
-#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_SHIFT 4
-#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PDN_HS_DES_MASK 0x00000010U
-
-/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/
-#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
-#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
-#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
-#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001
-#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0
-#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef USB3_0_FPD_POWER_PRSNT_OFFSET
#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080
-#undef CRL_APB_RST_LPD_TOP_OFFSET
-#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
-#undef CRL_APB_RST_LPD_TOP_OFFSET
-#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
-#undef USB3_1_FPD_POWER_PRSNT_OFFSET
-#define USB3_1_FPD_POWER_PRSNT_OFFSET 0XFF9E0080
+#undef USB3_0_FPD_PIPE_CLK_OFFSET
+#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET
#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
#undef CRF_APB_RST_FPD_TOP_OFFSET
#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
-#undef CRF_APB_RST_FPD_TOP_OFFSET
-#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
#undef DP_DP_PHY_RESET_OFFSET
#define DP_DP_PHY_RESET_OFFSET 0XFD4A0200
#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200
#undef USB3_0_XHCI_GFLADJ_OFFSET
#define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630
-#undef USB3_1_XHCI_GUSB2PHYCFG_OFFSET
-#define USB3_1_XHCI_GUSB2PHYCFG_OFFSET 0XFE30C200
-#undef USB3_1_XHCI_GFLADJ_OFFSET
-#define USB3_1_XHCI_GFLADJ_OFFSET 0XFE30C630
-#undef PCIE_ATTRIB_ATTR_25_OFFSET
-#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064
-#undef PCIE_ATTRIB_ATTR_7_OFFSET
-#define PCIE_ATTRIB_ATTR_7_OFFSET 0XFD48001C
-#undef PCIE_ATTRIB_ATTR_8_OFFSET
-#define PCIE_ATTRIB_ATTR_8_OFFSET 0XFD480020
-#undef PCIE_ATTRIB_ATTR_9_OFFSET
-#define PCIE_ATTRIB_ATTR_9_OFFSET 0XFD480024
-#undef PCIE_ATTRIB_ATTR_10_OFFSET
-#define PCIE_ATTRIB_ATTR_10_OFFSET 0XFD480028
-#undef PCIE_ATTRIB_ATTR_11_OFFSET
-#define PCIE_ATTRIB_ATTR_11_OFFSET 0XFD48002C
-#undef PCIE_ATTRIB_ATTR_12_OFFSET
-#define PCIE_ATTRIB_ATTR_12_OFFSET 0XFD480030
-#undef PCIE_ATTRIB_ATTR_13_OFFSET
-#define PCIE_ATTRIB_ATTR_13_OFFSET 0XFD480034
-#undef PCIE_ATTRIB_ATTR_14_OFFSET
-#define PCIE_ATTRIB_ATTR_14_OFFSET 0XFD480038
-#undef PCIE_ATTRIB_ATTR_15_OFFSET
-#define PCIE_ATTRIB_ATTR_15_OFFSET 0XFD48003C
-#undef PCIE_ATTRIB_ATTR_16_OFFSET
-#define PCIE_ATTRIB_ATTR_16_OFFSET 0XFD480040
-#undef PCIE_ATTRIB_ATTR_17_OFFSET
-#define PCIE_ATTRIB_ATTR_17_OFFSET 0XFD480044
-#undef PCIE_ATTRIB_ATTR_18_OFFSET
-#define PCIE_ATTRIB_ATTR_18_OFFSET 0XFD480048
-#undef PCIE_ATTRIB_ATTR_27_OFFSET
-#define PCIE_ATTRIB_ATTR_27_OFFSET 0XFD48006C
-#undef PCIE_ATTRIB_ATTR_50_OFFSET
-#define PCIE_ATTRIB_ATTR_50_OFFSET 0XFD4800C8
-#undef PCIE_ATTRIB_ATTR_105_OFFSET
-#define PCIE_ATTRIB_ATTR_105_OFFSET 0XFD4801A4
-#undef PCIE_ATTRIB_ATTR_106_OFFSET
-#define PCIE_ATTRIB_ATTR_106_OFFSET 0XFD4801A8
-#undef PCIE_ATTRIB_ATTR_107_OFFSET
-#define PCIE_ATTRIB_ATTR_107_OFFSET 0XFD4801AC
-#undef PCIE_ATTRIB_ATTR_108_OFFSET
-#define PCIE_ATTRIB_ATTR_108_OFFSET 0XFD4801B0
-#undef PCIE_ATTRIB_ATTR_109_OFFSET
-#define PCIE_ATTRIB_ATTR_109_OFFSET 0XFD4801B4
-#undef PCIE_ATTRIB_ATTR_34_OFFSET
-#define PCIE_ATTRIB_ATTR_34_OFFSET 0XFD480088
-#undef PCIE_ATTRIB_ATTR_53_OFFSET
-#define PCIE_ATTRIB_ATTR_53_OFFSET 0XFD4800D4
-#undef PCIE_ATTRIB_ATTR_41_OFFSET
-#define PCIE_ATTRIB_ATTR_41_OFFSET 0XFD4800A4
-#undef PCIE_ATTRIB_ATTR_97_OFFSET
-#define PCIE_ATTRIB_ATTR_97_OFFSET 0XFD480184
-#undef PCIE_ATTRIB_ATTR_100_OFFSET
-#define PCIE_ATTRIB_ATTR_100_OFFSET 0XFD480190
-#undef PCIE_ATTRIB_ATTR_101_OFFSET
-#define PCIE_ATTRIB_ATTR_101_OFFSET 0XFD480194
-#undef PCIE_ATTRIB_ATTR_37_OFFSET
-#define PCIE_ATTRIB_ATTR_37_OFFSET 0XFD480094
-#undef PCIE_ATTRIB_ATTR_93_OFFSET
-#define PCIE_ATTRIB_ATTR_93_OFFSET 0XFD480174
-#undef PCIE_ATTRIB_ID_OFFSET
-#define PCIE_ATTRIB_ID_OFFSET 0XFD480200
-#undef PCIE_ATTRIB_SUBSYS_ID_OFFSET
-#define PCIE_ATTRIB_SUBSYS_ID_OFFSET 0XFD480204
-#undef PCIE_ATTRIB_REV_ID_OFFSET
-#define PCIE_ATTRIB_REV_ID_OFFSET 0XFD480208
-#undef PCIE_ATTRIB_ATTR_24_OFFSET
-#define PCIE_ATTRIB_ATTR_24_OFFSET 0XFD480060
#undef PCIE_ATTRIB_ATTR_25_OFFSET
#define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064
-#undef PCIE_ATTRIB_ATTR_0_OFFSET
-#define PCIE_ATTRIB_ATTR_0_OFFSET 0XFD480000
-#undef PCIE_ATTRIB_ATTR_4_OFFSET
-#define PCIE_ATTRIB_ATTR_4_OFFSET 0XFD480010
-#undef PCIE_ATTRIB_ATTR_89_OFFSET
-#define PCIE_ATTRIB_ATTR_89_OFFSET 0XFD480164
-#undef PCIE_ATTRIB_ATTR_79_OFFSET
-#define PCIE_ATTRIB_ATTR_79_OFFSET 0XFD48013C
-#undef PCIE_ATTRIB_ATTR_43_OFFSET
-#define PCIE_ATTRIB_ATTR_43_OFFSET 0XFD4800AC
-#undef PCIE_ATTRIB_ATTR_48_OFFSET
-#define PCIE_ATTRIB_ATTR_48_OFFSET 0XFD4800C0
-#undef PCIE_ATTRIB_ATTR_46_OFFSET
-#define PCIE_ATTRIB_ATTR_46_OFFSET 0XFD4800B8
-#undef PCIE_ATTRIB_ATTR_47_OFFSET
-#define PCIE_ATTRIB_ATTR_47_OFFSET 0XFD4800BC
-#undef PCIE_ATTRIB_ATTR_44_OFFSET
-#define PCIE_ATTRIB_ATTR_44_OFFSET 0XFD4800B0
-#undef PCIE_ATTRIB_ATTR_45_OFFSET
-#define PCIE_ATTRIB_ATTR_45_OFFSET 0XFD4800B4
-#undef PCIE_ATTRIB_CB_OFFSET
-#define PCIE_ATTRIB_CB_OFFSET 0XFD48031C
-#undef PCIE_ATTRIB_ATTR_35_OFFSET
-#define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C
-#undef CRF_APB_RST_FPD_TOP_OFFSET
-#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
#undef SATA_AHCI_VENDOR_PP2C_OFFSET
#define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC
#undef SATA_AHCI_VENDOR_PP3C_OFFSET
#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0
#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U
+/*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/
+#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
+#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
+#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK
+#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
+#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0
+#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U
+
/*USB 0 sleep circuit reset*/
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
-/*USB 1 reset for control registers*/
-#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_DEFVAL
-#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT
-#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK
-#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_DEFVAL 0x00188FDF
-#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT 11
-#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK 0x00000800U
-
-/*This bit is used to choose between PIPE power present and 1'b1*/
-#undef USB3_1_FPD_POWER_PRSNT_OPTION_DEFVAL
-#undef USB3_1_FPD_POWER_PRSNT_OPTION_SHIFT
-#undef USB3_1_FPD_POWER_PRSNT_OPTION_MASK
-#define USB3_1_FPD_POWER_PRSNT_OPTION_DEFVAL
-#define USB3_1_FPD_POWER_PRSNT_OPTION_SHIFT 0
-#define USB3_1_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U
-
-/*USB 1 sleep circuit reset*/
-#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_DEFVAL
-#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT
-#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK
-#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_DEFVAL 0x00188FDF
-#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT 9
-#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK 0x00000200U
-
-/*USB 1 reset*/
-#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_DEFVAL
-#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT
-#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK
-#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_DEFVAL 0x00188FDF
-#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT 7
-#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK 0x00000080U
-
/*GEM 3 reset*/
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U
-/*PCIE config reset*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
-
-/*PCIE bridge block level reset (AXI interface)*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
-
/*Display Port block level reset (includes DPDMA)*/
#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U
-/*Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.*/
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6
-#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U
-
/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U
-/*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
- he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
- C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
- . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
- UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
- alue. Note: This field is valid only in device mode.*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10
-#define USB3_1_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U
-
-/*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
- of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
- time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
- ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
- off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
- ng hibernation. - This bit is valid only in device mode.*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9
-#define USB3_1_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U
-
-/*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
- _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
- to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
- ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
- n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
- d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
- d.*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8
-#define USB3_1_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U
-
-/*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
- Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
- 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
- in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
- active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_PHYSEL_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7
-#define USB3_1_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U
-
-/*Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
- figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
- ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
- r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
- t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
- g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
- when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6
-#define USB3_1_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U
-
-/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
- full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
- ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
- B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_FSINTF_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5
-#define USB3_1_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U
-
-/*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
- e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
- ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
- lected through DWC_USB3_HSPHY_INTERFACE.*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4
-#define USB3_1_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U
-
-/*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
- 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
- lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
- ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
- any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_PHYIF_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3
-#define USB3_1_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U
-
-/*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
- a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
- dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
- e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
- The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
- ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
- clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
- 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/
-#undef USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL
-#undef USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
-#undef USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL_MASK
-#define USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000
-#define USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0
-#define USB3_1_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U
-
-/*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
- alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
- _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
- TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
- riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
- cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
- uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
- ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
- RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/
-#undef USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL
-#undef USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
-#undef USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK
-#define USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000
-#define USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8
-#define USB3_1_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U
-
-/*Status Read value of PLL Lock*/
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
-#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4
-#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
-#define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4
+/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
+ ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U
/*Status Read value of PLL Lock*/
#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U
#define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4
-/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
- ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK
-#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905
-#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9
-#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U
-
-/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
- ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
- Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
- erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
- set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
- re size in bytes.; EP=0x0004; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL
-#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
-#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK
-#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL
-#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0
-#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU
-
-/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
- ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
- Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
- erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
- set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
- re size in bytes.; EP=0xFFF0; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL
-#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
-#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK
-#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL
-#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0
-#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU
-
-/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
- AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
- bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
- o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
- 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
- '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
- ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL
-#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
-#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK
-#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL
-#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0
-#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU
-
-/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
- AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
- bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
- o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
- 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
- '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
- ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL
-#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
-#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK
-#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL
-#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0
-#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU
-
-/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
- AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
- , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
- ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
- most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
- . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
- ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/
-#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL
-#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
-#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK
-#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL
-#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0
-#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU
-
-/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
- AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
- , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
- ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
- most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
- . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
- ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/
-#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL
-#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
-#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK
-#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL
-#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0
-#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU
-
-/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
- AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
- Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
- t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
- t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
- if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
- f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
- bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL
-#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
-#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK
-#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL
-#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0
-#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU
-
-/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
- AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
- Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
- t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
- t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
- if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
- f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
- bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/
-#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL
-#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
-#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK
-#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL
-#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0
-#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU
-
-/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
- AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
- , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
- ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
- most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
- . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
- ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/
-#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL
-#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
-#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK
-#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL
-#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0
-#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU
-
-/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
- AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
- , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
- ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
- most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
- . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
- ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/
-#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL
-#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
-#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK
-#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL
-#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0
-#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU
-
-/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
- AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
- Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
- refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
- R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
- refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
- ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
- permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
-#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL
-#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
-#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK
-#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL
-#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0
-#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU
-
-/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
- AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
- tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
- Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
- refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
- R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
- refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
- ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
- permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
-#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL
-#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
-#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK
-#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL
-#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0
-#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU
-
-/*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
- to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL
-#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
-#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK
-#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138
-#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8
-#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U
-
-/*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
- state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
- 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL
-#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
-#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK
-#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138
-#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3
-#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U
-
-/*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
- 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
- tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
- gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/
-#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL
-#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
-#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK
-#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02
-#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4
-#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U
-
-/*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
- lity.; EP=0x009C; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL
-#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
-#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK
-#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02
-#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8
-#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U
-
-/*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
- ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/
-#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL
-#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
-#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK
-#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL
-#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0
-#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU
-
-/*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non
- osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/
-#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL
-#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
-#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK
-#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248
-#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0
-#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU
-
-/*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
- a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
- completion header credits must be <= 80; EP=0x0004; RP=0x000C*/
-#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL
-#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
-#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK
-#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248
-#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7
-#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U
-
-/*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data
- redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
- d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
- less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/
-#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL
-#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
-#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK
-#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL
-#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0
-#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU
-
-/*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less
- han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/
-#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL
-#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
-#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK
-#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL
-#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0
-#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU
-
-/*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
- 0*/
-#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL
-#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
-#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK
-#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04
-#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15
-#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U
-
-/*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL
-#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
-#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK
-#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04
-#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14
-#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U
-
-/*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
- cap structure; EP=0x0003; RP=0x0003*/
-#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL
-#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
-#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK
-#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04
-#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12
-#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U
-
-/*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
- mber of brams configured for transmit; EP=0x001C; RP=0x001C*/
-#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL
-#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
-#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK
-#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04
-#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7
-#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U
-
-/*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
- d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/
-#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL
-#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
-#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK
-#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04
-#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0
-#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU
-
-/*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
- 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL
-#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
-#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK
-#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100
-#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0
-#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU
-
-/*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
- ty.; EP=0x0048; RP=0x0060*/
-#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL
-#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
-#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK
-#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48
-#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0
-#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU
-
-/*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
- to Cap structure; EP=0x0000; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U
-
-/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
- he management port.; EP=0x0001; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U
-
-/*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
- ity.; EP=0x0060; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU
-
-/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
- he management port.; EP=0x0001; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
-#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8
-#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U
-
-/*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/
-#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL
-#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
-#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK
-#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104
-#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0
-#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU
-
-/*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
- 4; RP=0x0004*/
-#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL
-#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
-#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK
-#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104
-#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6
-#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U
-
-/*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL
-#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
-#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK
-#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0
-#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6
-#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U
-
-/*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message
- LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
- Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
- EP=0x0000; RP=0x07FF*/
-#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL
-#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
-#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK
-#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000
-#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5
-#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U
-
-/*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL
-#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
-#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK
-#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000
-#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1
-#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U
-
-/*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
- Required for Root.; EP=0x0000; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U
-
-/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
- gister.; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
-#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14
-#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U
-
-/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
- _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL
-#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
-#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK
-#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000
-#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15
-#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U
-
-/*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
- TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
- 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL
-#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
-#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK
-#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000
-#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0
-#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU
-
-/*Device ID for the the PCIe Cap Structure Device ID field*/
-#undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL
-#undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
-#undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK
-#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024
-#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0
-#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU
-
-/*Vendor ID for the PCIe Cap Structure Vendor ID field*/
-#undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL
-#undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
-#undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK
-#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024
-#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16
-#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U
-
-/*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/
-#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL
-#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
-#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK
-#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007
-#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0
-#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU
-
-/*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/
-#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL
-#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
-#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK
-#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007
-#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16
-#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U
-
-/*Revision ID for the the PCIe Cap Structure*/
-#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL
-#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
-#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK
-#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL
-#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0
-#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU
-
-/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
- 8000; RP=0x8000*/
-#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL
-#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
-#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK
-#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL
-#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0
-#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU
-
-/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
- 0005; RP=0x0006*/
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK
-#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905
-#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0
-#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU
-
-/*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK
-#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905
-#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8
-#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U
-
-/*Indicates that the core is capable of generating ECRC. Value transferred to bit 5 of the AER Capabilities and Control Registe
- .; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE_DEFVAL
-#undef PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE_SHIFT
-#undef PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE_MASK
-#define PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE_DEFVAL 0x00000003
-#define PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE_SHIFT 1
-#define PCIE_ATTRIB_ATTR_0_ATTR_AER_CAP_ECRC_GEN_CAPABLE_MASK 0x00000002U
-
-/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
- he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
- ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL
-#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
-#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK
-#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000
-#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12
-#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U
-
-/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
- he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
- ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL
-#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
-#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK
-#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000
-#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12
-#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U
-
-/*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
- 0x0140; RP=0x0140*/
-#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL
-#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
-#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK
-#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281
-#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1
-#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU
-
-/*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL
-#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
-#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK
-#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000
-#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5
-#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U
-
-/*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
- the management port.; EP=0x0001; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL
-#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
-#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK
-#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100
-#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8
-#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U
-
-/*MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note
- hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
-#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT
-#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK
-#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL
-#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0
-#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU
-
-/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001;
- P=0x0000*/
-#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
-#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
-#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
-#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
-#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
-#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU
-
-/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000;
- P=0x0000*/
-#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
-#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT
-#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK
-#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL
-#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0
-#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU
-
-/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
- 0x0001; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
-#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
-#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK
-#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
-#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0
-#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU
-
-/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP
- 0x1000; RP=0x0000*/
-#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL
-#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT
-#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK
-#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000
-#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3
-#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U
-
-/*DT837748 Enable*/
-#undef PCIE_ATTRIB_CB_CB1_DEFVAL
-#undef PCIE_ATTRIB_CB_CB1_SHIFT
-#undef PCIE_ATTRIB_CB_CB1_MASK
-#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001
-#define PCIE_ATTRIB_CB_CB1_SHIFT 1
-#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U
-
-/*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc
- ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/
-#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL
-#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT
-#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK
-#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD
-#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12
-#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U
-
-/*PCIE control block level reset*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
-
/*CIBGMN: COMINIT Burst Gap Minimum.*/
#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL
#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U
#undef CRL_APB_RST_LPD_TOP_OFFSET
#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
-#undef CRL_APB_RST_LPD_TOP_OFFSET
-#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET
#define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230
#undef CRF_APB_RST_FPD_TOP_OFFSET
#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
-#undef CRF_APB_RST_FPD_TOP_OFFSET
-#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
#define DP_DP_TX_PHY_POWER_DOWN_OFFSET 0XFD4A0238
#undef DP_DP_PHY_RESET_OFFSET
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U
-/*USB 1 reset for control registers*/
-#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_DEFVAL
-#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT
-#undef CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK
-#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_DEFVAL 0x00188FDF
-#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_SHIFT 11
-#define CRL_APB_RST_LPD_TOP_USB1_APB_RESET_MASK 0x00000800U
-
-/*USB 1 sleep circuit reset*/
-#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_DEFVAL
-#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT
-#undef CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK
-#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_DEFVAL 0x00188FDF
-#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_SHIFT 9
-#define CRL_APB_RST_LPD_TOP_USB1_HIBERRESET_MASK 0x00000200U
-
-/*USB 1 reset*/
-#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_DEFVAL
-#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT
-#undef CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK
-#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_DEFVAL 0x00188FDF
-#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_SHIFT 7
-#define CRL_APB_RST_LPD_TOP_USB1_CORERESET_MASK 0x00000080U
-
/*GEM 3 reset*/
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1
#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U
-/*PCIE config reset*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19
-#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U
-
-/*PCIE control block level reset*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17
-#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U
-
-/*PCIE bridge block level reset (AXI interface)*/
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
-#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18
-#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U
-
/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
ane0 Bits [3:2] - lane 1*/
#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE
#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16
#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U
+#undef CRF_APB_RST_FPD_TOP_OFFSET
+#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100
+#undef CRL_APB_RST_LPD_TOP_OFFSET
+#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C
+#undef FPD_SLCR_AFI_FS_OFFSET
+#define FPD_SLCR_AFI_FS_OFFSET 0XFD615000
+#undef LPD_SLCR_AFI_FS_OFFSET
+#define LPD_SLCR_AFI_FS_OFFSET 0XFF419000
+#undef AFIFM0_AFIFM_RDCTRL_OFFSET
+#define AFIFM0_AFIFM_RDCTRL_OFFSET 0XFD360000
+#undef AFIFM1_AFIFM_RDCTRL_OFFSET
+#define AFIFM1_AFIFM_RDCTRL_OFFSET 0XFD370000
+#undef AFIFM2_AFIFM_RDCTRL_OFFSET
+#define AFIFM2_AFIFM_RDCTRL_OFFSET 0XFD380000
+#undef AFIFM3_AFIFM_RDCTRL_OFFSET
+#define AFIFM3_AFIFM_RDCTRL_OFFSET 0XFD390000
+#undef AFIFM4_AFIFM_RDCTRL_OFFSET
+#define AFIFM4_AFIFM_RDCTRL_OFFSET 0XFD3A0000
+#undef AFIFM5_AFIFM_RDCTRL_OFFSET
+#define AFIFM5_AFIFM_RDCTRL_OFFSET 0XFD3B0000
+#undef AFIFM6_AFIFM_RDCTRL_OFFSET
+#define AFIFM6_AFIFM_RDCTRL_OFFSET 0XFF9B0000
+#undef AFIFM0_AFIFM_WRCTRL_OFFSET
+#define AFIFM0_AFIFM_WRCTRL_OFFSET 0XFD360014
+#undef AFIFM1_AFIFM_WRCTRL_OFFSET
+#define AFIFM1_AFIFM_WRCTRL_OFFSET 0XFD370014
+#undef AFIFM2_AFIFM_WRCTRL_OFFSET
+#define AFIFM2_AFIFM_WRCTRL_OFFSET 0XFD380014
+#undef AFIFM3_AFIFM_WRCTRL_OFFSET
+#define AFIFM3_AFIFM_WRCTRL_OFFSET 0XFD390014
+#undef AFIFM4_AFIFM_WRCTRL_OFFSET
+#define AFIFM4_AFIFM_WRCTRL_OFFSET 0XFD3A0014
+#undef AFIFM5_AFIFM_WRCTRL_OFFSET
+#define AFIFM5_AFIFM_WRCTRL_OFFSET 0XFD3B0014
+#undef AFIFM6_AFIFM_WRCTRL_OFFSET
+#define AFIFM6_AFIFM_WRCTRL_OFFSET 0XFF9B0014
#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118
#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120
+/*AF_FM0 block level reset*/
+#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK
+#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7
+#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 0x00000080U
+
+/*AF_FM1 block level reset*/
+#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK
+#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8
+#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 0x00000100U
+
+/*AF_FM2 block level reset*/
+#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK
+#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9
+#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 0x00000200U
+
+/*AF_FM3 block level reset*/
+#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK
+#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10
+#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 0x00000400U
+
+/*AF_FM4 block level reset*/
+#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK
+#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11
+#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 0x00000800U
+
+/*AF_FM5 block level reset*/
+#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK
+#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12
+#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 0x00001000U
+
+/*AFI FM 6*/
+#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK
+#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19
+#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 0x00080000U
+
+/*Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
+ : 128-bit AXI data width 11: reserved*/
+#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL
+#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT
+#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK
+#define FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x00000A00
+#define FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8
+#define FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300U
+
+/*Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
+ : 128-bit AXI data width 11: reserved*/
+#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL
+#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT
+#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK
+#define FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x00000A00
+#define FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10
+#define FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000C00U
+
+/*Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit AXI data width (default) 01: 64-bit AXI data width 1
+ : 128-bit AXI data width 11: reserved*/
+#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL
+#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT
+#undef LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK
+#define LPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x00000200
+#define LPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8
+#define LPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300U
+
+/*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled*/
+#undef AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
+#define AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM0_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled*/
+#undef AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
+#define AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM1_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled*/
+#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
+#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM2_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled*/
+#undef AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
+#define AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM3_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled*/
+#undef AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
+#define AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM4_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled*/
+#undef AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
+#define AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM5_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Read Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 128
+ bit enabled*/
+#undef AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_MASK
+#define AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM6_AFIFM_RDCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled*/
+#undef AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
+#define AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM0_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled*/
+#undef AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
+#define AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM1_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled*/
+#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
+#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM2_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled*/
+#undef AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
+#define AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM3_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled*/
+#undef AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
+#define AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM4_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled*/
+#undef AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
+#define AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM5_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
+/*Configures the Write Channel Fabric interface width. 2'b11 : Reserved 2'b10 : 32-bit Fabric 2'b01 : 64-bit enabled 2'b00 : 12
+ -bit enabled*/
+#undef AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL
+#undef AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT
+#undef AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_MASK
+#define AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_DEFVAL 0x000003B0
+#define AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_SHIFT 0
+#define AFIFM6_AFIFM_WRCTRL_FABRIC_WIDTH_MASK 0x00000003U
+
/*Power-up Request Interrupt Enable for PL*/
#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL
#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
int psu_init ();
unsigned long psu_ps_pl_isolation_removal_data();
unsigned long psu_ps_pl_reset_config_data();
+ int psu_protection();
+ int psu_fpd_protection();
+ int psu_ocm_protection();
+ int psu_ddr_protection();
+ int psu_lpd_protection();
+ int psu_protection_lock();
+ unsigned long psu_apply_master_tz();
#ifdef __cplusplus
}
#endif
projects / thirdparty / u-boot.git / commitdiff
