drm/i915/ltphy: Enable SSC during port clock programming

We enable SSC when we program PORT_CLOCK_CTL register. We logically
determine if ssc is enabled or not while we calculate our state.

Bspec: 74492, 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-12-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 892dea3b975feac2466fd54b5b2b455c7d163011..1b7d92fff834ccea2ed7d0ac93f8b460f42e1db8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -16,6 +16,7 @@
 #include "intel_hdmi.h"
 #include "intel_lt_phy.h"
 #include "intel_lt_phy_regs.h"
+#include "intel_panel.h"
 #include "intel_psr.h"
 #include "intel_tc.h"
 
@@ -1109,6 +1110,12 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
        else
                val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
 
+        /* DP2.0 10G and 20G rates enable MPLLA*/
+       if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
+               val |= XELPDP_SSC_ENABLE_PLLA;
+       else
+               val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+
        intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
                     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
                     XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
@@ -1211,6 +1218,23 @@ intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
        return NULL;
 }
 
+static bool
+intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
+                               struct intel_encoder *encoder)
+{
+       struct intel_display *display = to_intel_display(encoder);
+
+       if (intel_crtc_has_dp_encoder(crtc_state)) {
+               if (intel_panel_use_ssc(display)) {
+                       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+                       return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
+               }
+       }
+
+       return false;
+}
+
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
                            struct intel_encoder *encoder)
@@ -1229,6 +1253,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
                                if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
                                        crtc_state->dpll_hw_state.ltpll.config[2] = 1;
                        }
+                       crtc_state->dpll_hw_state.ltpll.ssc_enabled =
+                               intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
                        return 0;
                }
        }