* Harvested from Cadence driver.
*/
-#ifndef __XDFETH_H__
-#define __XDFETH_H__
-
-#define XDFETH_RX_BUF_SIZE 128
-
-#define XDFETH_RBQ_LENGTH 128
-#define XDFETH_TBQ_LENGTH 128
-
-#define XDFETH_MDIO_ENABLED (GEM_MDIO_EN)
-
-#define XDFETH_DEF_PCLK_DIV (MDC_DIV_32)
-
-#define XDFETH_DEF_AHB_WIDTH (AMBA_AHB_32)
-
-#define XDFETH_DEF_DUPLEX (GEM_FULL_DUPLEX)
-
-#define XDFETH_DEF_SPEED (SPEED_100M)
-
-#define XDFETH_DEF_LOOP (LB_NONE)
-
-#define XDFETH_READ_SNAP (1<<14) /* Read snapshot register */
-#define XDFETH_TAKE_SNAP (1<<13) /* Take a snapshot */
-#define XDFETH_TX_0Q_PAUSE (1<<12) /* Transmit zero quantum pause frame */
-#define XDFETH_TX_PAUSE (1<<11) /* Transmit pause frame */
-#define XDFETH_TX_HALT (1<<10) /* Halt transmission after curr frame */
-#define XDFETH_TX_START (1<<9) /* Start tx (tx_go) */
-#define XDFETH_STATS_WR_EN (1<<7) /* Enable writing to stat registers */
-#define XDFETH_STATS_INC (1<<6) /* Increment statistic registers */
-#define XDFETH_STATS_CLR (1<<5) /* Clear statistic registers */
-#define XDFETH_MDIO_EN (1<<4) /* Enable MDIO port */
-#define XDFETH_TX_EN (1<<3) /* Enable transmit circuits */
-#define XDFETH_RX_EN (1<<2) /* Enable receive circuits */
-#define XDFETH_LB_MAC (1<<1) /* Perform local loopback at MAC */
-#define XDFETH_LB_PHY (1<<0) /* Perform ext loopback through PHY */
-
-#define XDFETH_RX_NO_PAUSE (1<<23) /* Do not copy pause frames to memory */
-#define XDFETH_AHB_WIDTH1 (1<<22) /* Bit 1 for defining AHB width */
-#define XDFETH_AHB_WIDTH0 (1<<21) /* Bit 0 for defining AHB width */
-#define XDFETH_MDC_DIV2 (1<<20) /* PCLK divisor for MDC, bit 2 */
-#define XDFETH_MDC_DIV1 (1<<19) /* PCLK divisor for MDC, bit 1 */
-#define XDFETH_MDC_DIV0 (1<<18) /* PCLK divisor for MDC, bit 0 */
-#define XDFETH_RX_NO_FCS (1<<17) /* Discard FCS from received frames. */
-#define XDFETH_RX_LEN_CHK (1<<16) /* Receive length check. */
-#define XDFETH_RX_OFFSET_BASE 14 /* Pos of LSB for rx buffer offsets. */
-#define XDFETH_RX_OFFSET1 (1<<(GEM_RX_OFFSET_BASE + 1)) /* RX offset bit 1 */
-#define XDFETH_RX_OFFSET0 (1<<GEM_RX_OFFSET_BASE) /* RX offset bit 0 */
-#define XDFETH_RX_PAUSE_EN (1<<13) /* Enable pause reception */
-#define XDFETH_RETRY_TEST (1<<12) /* Retry test for speeding up debug */
-#define XDFETH_PCS_SEL (1<<11) /* Select PCS */
-#define XDFETH_GIG_MODE (1<<10) /* Gigabit mode enable */
-#define XDFETH_EAM_EN (1<<9) /* External address match enable */
-#define XDFETH_FRAME_1536 (1<<8) /* Enable 1536 byte frames reception */
-#define XDFETH_UNICAST_EN (1<<7) /* Receive unicast hash frames */
-#define XDFETH_MULTICAST_EN (1<<6) /* Receive multicast hash frames */
-#define XDFETH_NO_BROADCAST (1<<5) /* Do not receive broadcast frames */
-#define XDFETH_COPY_ALL (1<<4) /* Copy all frames */
-#define XDFETH_RX_JUMBO (1<<3) /* Allow jumbo frame reception */
-#define XDFETH_VLAN_ONLY (1<<2) /* Receive only VLAN frames */
-#define XDFETH_FULL_DUPLEX (1<<1) /* Enable full duplex */
-#define XDFETH_SPEED_100 (1<<0) /* Set to 100Mb mode */
-
-#define XDFETH_PHY_IDLE (1<<2) /* PHY management is idle */
-#define XDFETH_MDIO_IN (1<<1) /* Status of mdio_in pin */
-#define XDFETH_LINK_STATUS (1<<0) /* Status of link pin */
-
-#define XDFETH_TX_HRESP (1<<8) /* Transmit hresp not OK */
-#define XDFETH_LATE_COL (1<<7) /* Late collision */
-#define XDFETH_TX_URUN (1<<6) /* Transmit underrun occurred */
-#define XDFETH_TX_COMPLETE (1<<5) /* Transmit completed OK */
-#define XDFETH_TX_BUF_EXH (1<<4) /* Transmit buffs exhausted mid frame */
-#define XDFETH_TX_GO (1<<3) /* Status of tx_go internal variable */
-#define XDFETH_TX_RETRY_EXC (1<<2) /* Retry limit exceeded */
-#define XDFETH_TX_COL (1<<1) /* Collision occurred during frame tx */
-#define XDFETH_TX_USED (1<<0) /* Used bit read in tx buffer */
-
-#define XDFETH_RX_HRESP (1<<3) /* Receive hresp not OK */
-#define XDFETH_RX_ORUN (1<<2) /* Receive overrun occurred */
-#define XDFETH_RX_DONE (1<<1) /* Frame successfully received */
-#define XDFETH_RX_BUF_USED (1<<0) /* Receive buffer used bit read */
-
-#define XDFETH_IRQ_PCS_AN (1<<16) /* PCS autonegotiation complete */
-#define XDFETH_IRQ_EXT_INT (1<<15) /* External interrupt pin triggered */
-#define XDFETH_IRQ_PAUSE_TX (1<<14) /* Pause frame transmitted */
-#define XDFETH_IRQ_PAUSE_0 (1<<13) /* Pause time has reached zero */
-#define XDFETH_IRQ_PAUSE_RX (1<<12) /* Pause frame received */
-#define XDFETH_IRQ_HRESP (1<<11) /* hresp not ok */
-#define XDFETH_IRQ_RX_ORUN (1<<10) /* Receive overrun occurred */
-#define XDFETH_IRQ_PCS_LINK (1<<9) /* Status of PCS link changed */
-#define XDFETH_IRQ_TX_DONE (1<<7) /* Frame transmitted ok */
-#define XDFETH_IRQ_TX_ERROR (1<<6) /* Transmit err occurred or no buffers*/
-#define XDFETH_IRQ_RETRY_EXC (1<<5) /* Retry limit exceeded */
-#define XDFETH_IRQ_TX_URUN (1<<4) /* Transmit underrun occurred */
-#define XDFETH_IRQ_TX_USED (1<<3) /* Tx buffer used bit read */
-#define XDFETH_IRQ_RX_USED (1<<2) /* Rx buffer used bit read */
-#define XDFETH_IRQ_RX_DONE (1<<1) /* Frame received ok */
-#define XDFETH_IRQ_MAN_DONE (1<<0) /* PHY management operation complete */
-#define XDFETH_IRQ_ALL (0xFFFFFFFF)/* Everything! */
-
-#define XDFETH_TBQE_USED (1<<31) /* Used bit. */
-#define XDFETH_TBQE_WRAP (1<<30) /* Wrap bit */
-#define XDFETH_TBQE_RETRY_EXC (1<<29) /* Retry limit exceeded. */
-#define XDFETH_TBQE_URUN (1<<28) /* Transmit underrun occurred. */
-#define XDFETH_TBQE_BUF_EXH (1<<27) /* Buffers exhausted mid frame. */
-#define XDFETH_TBQE_LATE_COL (1<<26) /* Late collision. */
-#define XDFETH_TBQE_NO_CRC (1<<16) /* No CRC */
-#define XDFETH_TBQE_LAST_BUF (1<<15) /* Last buffer */
-#define XDFETH_TBQE_LEN_MASK (0x3FFF) /* Mask for length field */
-#define XDFETH_TX_MAX_LEN (0x3FFF) /* Maximum transmit length value */
-#define XDFETH_TBQE_DUMMY (0x8000BFFF)/* Dummy value to check for free buffer*/
-
-#define XDFETH_RBQE_BROADCAST (1<<31) /* Broadcast frame */
-#define XDFETH_RBQE_MULTICAST (1<<30) /* Multicast hashed frame */
-#define XDFETH_RBQE_UNICAST (1<<29) /* Unicast hashed frame */
-#define XDFETH_RBQE_EXT_ADDR (1<<28) /* External address match */
-#define XDFETH_RBQE_SPEC_MATCH (1<<27) /* Specific address matched */
-#define XDFETH_RBQE_SPEC_BASE (25) /* Pos for base of specific match */
-#define XDFETH_RBQE_SPEC_MAT1 (1<<(RBQE_SPEC_BASE + 1))
-#define XDFETH_RBQE_SPEC_MAT0 (1<<RBQE_SPEC_BASE)
-#define XDFETH_RBQE_TYPE_MATCH (1<<24) /* Type ID matched */
-#define XDFETH_RBQE_TYPE_BASE (22) /* Position for base of type id match */
-#define XDFETH_RBQE_TYPE_MAT1 (1<<(RBQE_TYPE_BASE + 1))
-#define XDFETH_RBQE_TYPE_MAT0 (1<<RBQE_TYPE_BASE)
-#define XDFETH_RBQE_VLAN (1<<21) /* VLAN tagged */
-#define XDFETH_RBQE_PRIORITY (1<<20) /* Priority tagged */
-#define XDFETH_RBQE_VLAN_BASE (17) /* Position for base of VLAN priority */
-#define XDFETH_RBQE_VLAN_P2 (1<<(RBQE_VLAN_BASE+2))
-#define XDFETH_RBQE_VLAN_P1 (1<<(RBQE_VLAN_BASE+1))
-#define XDFETH_RBQE_VLAN_P0 (1<<RBQE_VLAN_BASE)
-#define XDFETH_RBQE_CFI (1<<16) /* CFI frame */
-#define XDFETH_RBQE_EOF (1<<15) /* End of frame. */
-#define XDFETH_RBQE_SOF (1<<14) /* Start of frame. */
-#define XDFETH_RBQE_LEN_MASK (0x3FFF) /* Mask for the length field. */
-#define XDFETH_RBQE_WRAP (1<<1) /* Wrap bit.. */
-#define XDFETH_RBQE_USED (1<<0) /* Used bit.. */
-#define XDFETH_RBQE_ADD_MASK (0xFFFFFFFC)/* Mask for address */
-
-#define XDFETH_REV_ID_MODEL_MASK (0x000F0000) /* Model ID */
-#define XDFETH_REV_ID_MODEL_BASE (16) /* For Shifting */
-#define XDFETH_REV_ID_REG_MODEL (0x00020000) /* GEM module ID */
-#define XDFETH_REV_ID_REV_MASK (0x0000FFFF) /* Revision ID */
-
-#define XDFETH_NET_CONTROL (0x00)
-#define XDFETH_NET_CONFIG (0x04)
-#define XDFETH_NET_STATUS (0x08)
-#define XDFETH_USER_IO (0x0C)
-#define XDFETH_TX_STATUS (0x14)
-#define XDFETH_RX_QPTR (0x18)
-#define XDFETH_TX_QPTR (0x1C)
-#define XDFETH_RX_STATUS (0x20)
-#define XDFETH_IRQ_STATUS (0x24)
-#define XDFETH_IRQ_ENABLE (0x28)
-#define XDFETH_IRQ_DISABLE (0x2C)
-#define XDFETH_IRQ_MASK (0x30)
-#define XDFETH_PHY_MAN (0x34)
-#define XDFETH_RX_PAUSE_TIME (0x38)
-#define XDFETH_TX_PAUSE_QUANT (0x3C)
-
-#define XDFETH_HASH_BOT (0x80)
-#define XDFETH_HASH_TOP (0x84)
-#define XDFETH_LADDR1_BOT (0x88)
-#define XDFETH_LADDR1_TOP (0x8C)
-#define XDFETH_LADDR2_BOT (0x90)
-#define XDFETH_LADDR2_TOP (0x94)
-#define XDFETH_LADDR3_BOT (0x98)
-#define XDFETH_LADDR3_TOP (0x9C)
-#define XDFETH_LADDR4_BOT (0xA0)
-#define XDFETH_LADDR4_TOP (0xA4)
-#define XDFETH_ID_CHECK1 (0xA8)
-#define XDFETH_ID_CHECK2 (0xAC)
-#define XDFETH_ID_CHECK3 (0xB0)
-#define XDFETH_ID_CHECK4 (0xB4)
-#define XDFETH_REV_ID (0xFC)
-
-#define XDFETH_OCT_TX_BOT (0x100)
-#define XDFETH_OCT_TX_TOP (0x104)
-#define XDFETH_STATS_FRAMES_TX (0x108)
-#define XDFETH_BROADCAST_TX (0x10C)
-#define XDFETH_MULTICAST_TX (0x110)
-#define XDFETH_STATS_PAUSE_TX (0x114)
-#define XDFETH_FRAME64_TX (0x118)
-#define XDFETH_FRAME65_TX (0x11C)
-#define XDFETH_FRAME128_TX (0x120)
-#define XDFETH_FRAME256_TX (0x124)
-#define XDFETH_FRAME512_TX (0x128)
-#define XDFETH_FRAME1024_TX (0x12C)
-#define XDFETH_FRAME1519_TX (0x130)
-#define XDFETH_STATS_TX_URUN (0x134)
-#define XDFETH_STATS_SINGLE_COL (0x138)
-#define XDFETH_STATS_MULTI_COL (0x13C)
-#define XDFETH_STATS_EXCESS_COL (0x140)
-#define XDFETH_STATS_LATE_COL (0x144)
-#define XDFETH_STATS_DEF_TX (0x148)
-#define XDFETH_STATS_CRS_ERRORS (0x14C)
-#define XDFETH_OCT_RX_BOT (0x150)
-#define XDFETH_OCT_RX_TOP (0x154)
-#define XDFETH_STATS_FRAMES_RX (0x158)
-#define XDFETH_BROADCAST_RX (0x15C)
-#define XDFETH_MULTICAST_RX (0x160)
-#define XDFETH_STATS_PAUSE_RX (0x164)
-#define XDFETH_FRAME64_RX (0x168)
-#define XDFETH_FRAME65_RX (0x16C)
-#define XDFETH_FRAME128_RX (0x170)
-#define XDFETH_FRAME256_RX (0x174)
-#define XDFETH_FRAME512_RX (0x178)
-#define XDFETH_FRAME1024_RX (0x17C)
-#define XDFETH_FRAME1519_RX (0x180)
-#define XDFETH_STATS_USIZE_FRAMES (0x184)
-#define XDFETH_STATS_EXCESS_LEN (0x188)
-#define XDFETH_STATS_JABBERS (0x18C)
-#define XDFETH_STATS_FCS_ERRORS (0x190)
-#define XDFETH_STATS_LENGTH_ERRORS (0x194)
-#define XDFETH_STATS_RX_SYM_ERR (0x198)
-#define XDFETH_STATS_ALIGN_ERRORS (0x19C)
-#define XDFETH_STATS_RX_RES_ERR (0x1a0)
-#define XDFETH_STATS_RX_ORUN (0x1a4)
-
-#define XDFETH_REG_TOP (0x23C)
+#ifndef __XZYNQETH_H__
+#define __XZYNQETH_H__
+
+#define XZYNQETH_RX_BUF_SIZE 128
+
+#define XZYNQETH_RBQ_LENGTH 128
+#define XZYNQETH_TBQ_LENGTH 128
+
+#define XZYNQETH_MDIO_ENABLED (GEM_MDIO_EN)
+
+#define XZYNQETH_DEF_PCLK_DIV (MDC_DIV_32)
+
+#define XZYNQETH_DEF_AHB_WIDTH (AMBA_AHB_32)
+
+#define XZYNQETH_DEF_DUPLEX (GEM_FULL_DUPLEX)
+
+#define XZYNQETH_DEF_SPEED (SPEED_100M)
+
+#define XZYNQETH_DEF_LOOP (LB_NONE)
+
+#define XZYNQETH_READ_SNAP (1<<14) /* Read snapshot register */
+#define XZYNQETH_TAKE_SNAP (1<<13) /* Take a snapshot */
+/* Transmit zero quantum pause frame */
+#define XZYNQETH_TX_0Q_PAUSE (1<<12)
+#define XZYNQETH_TX_PAUSE (1<<11) /* Transmit pause frame */
+/* Halt transmission after curr frame */
+#define XZYNQETH_TX_HALT (1<<10)
+#define XZYNQETH_TX_START (1<<9) /* Start tx (tx_go) */
+/* Enable writing to stat registers */
+#define XZYNQETH_STATS_WR_EN (1<<7)
+#define XZYNQETH_STATS_INC (1<<6) /* Increment statistic registers */
+#define XZYNQETH_STATS_CLR (1<<5) /* Clear statistic registers */
+#define XZYNQETH_MDIO_EN (1<<4) /* Enable MDIO port */
+#define XZYNQETH_TX_EN (1<<3) /* Enable transmit circuits */
+#define XZYNQETH_RX_EN (1<<2) /* Enable receive circuits */
+#define XZYNQETH_LB_MAC (1<<1) /* Perform local loopback at MAC */
+/* Perform ext loopback through PHY */
+#define XZYNQETH_LB_PHY (1<<0)
+
+/* Do not copy pause frames to memory */
+#define XZYNQETH_RX_NO_PAUSE (1<<23)
+#define XZYNQETH_AHB_WIDTH1 (1<<22) /* Bit 1 for defining AHB width */
+#define XZYNQETH_AHB_WIDTH0 (1<<21) /* Bit 0 for defining AHB width */
+#define XZYNQETH_MDC_DIV2 (1<<20) /* PCLK divisor for MDC, bit 2 */
+#define XZYNQETH_MDC_DIV1 (1<<19) /* PCLK divisor for MDC, bit 1 */
+#define XZYNQETH_MDC_DIV0 (1<<18) /* PCLK divisor for MDC, bit 0 */
+/* Discard FCS from received frames. */
+#define XZYNQETH_RX_NO_FCS (1<<17)
+#define XZYNQETH_RX_LEN_CHK (1<<16) /* Receive length check. */
+/* Pos of LSB for rx buffer offsets. */
+#define XZYNQETH_RX_OFFSET_BASE 14
+/* RX offset bit 1 */
+#define XZYNQETH_RX_OFFSET1 (1<<(GEM_RX_OFFSET_BASE + 1))
+/* RX offset bit 0 */
+#define XZYNQETH_RX_OFFSET0 (1<<GEM_RX_OFFSET_BASE)
+#define XZYNQETH_RX_PAUSE_EN (1<<13) /* Enable pause reception */
+/* Retry test for speeding up debug */
+#define XZYNQETH_RETRY_TEST (1<<12)
+#define XZYNQETH_PCS_SEL (1<<11) /* Select PCS */
+#define XZYNQETH_GIG_MODE (1<<10) /* Gigabit mode enable */
+#define XZYNQETH_EAM_EN (1<<9) /* External address match enable */
+/* Enable 1536 byte frames reception */
+#define XZYNQETH_FRAME_1536 (1<<8)
+#define XZYNQETH_UNICAST_EN (1<<7) /* Receive unicast hash frames */
+#define XZYNQETH_MULTICAST_EN (1<<6) /* Receive multicast hash frames */
+/* Do not receive broadcast frames */
+#define XZYNQETH_NO_BROADCAST (1<<5)
+#define XZYNQETH_COPY_ALL (1<<4) /* Copy all frames */
+#define XZYNQETH_RX_JUMBO (1<<3) /* Allow jumbo frame reception */
+#define XZYNQETH_VLAN_ONLY (1<<2) /* Receive only VLAN frames */
+#define XZYNQETH_FULL_DUPLEX (1<<1) /* Enable full duplex */
+#define XZYNQETH_SPEED_100 (1<<0) /* Set to 100Mb mode */
+
+#define XZYNQETH_PHY_IDLE (1<<2) /* PHY management is idle */
+#define XZYNQETH_MDIO_IN (1<<1) /* Status of mdio_in pin */
+#define XZYNQETH_LINK_STATUS (1<<0) /* Status of link pin */
+
+#define XZYNQETH_TX_HRESP (1<<8) /* Transmit hresp not OK */
+#define XZYNQETH_LATE_COL (1<<7) /* Late collision */
+#define XZYNQETH_TX_URUN (1<<6) /* Transmit underrun occurred */
+#define XZYNQETH_TX_COMPLETE (1<<5) /* Transmit completed OK */
+/* Transmit buffs exhausted mid frame */
+#define XZYNQETH_TX_BUF_EXH (1<<4)
+/* Status of tx_go internal variable */
+#define XZYNQETH_TX_GO (1<<3)
+#define XZYNQETH_TX_RETRY_EXC (1<<2) /* Retry limit exceeded */
+/* Collision occurred during frame tx */
+#define XZYNQETH_TX_COL (1<<1)
+#define XZYNQETH_TX_USED (1<<0) /* Used bit read in tx buffer */
+
+#define XZYNQETH_RX_HRESP (1<<3) /* Receive hresp not OK */
+#define XZYNQETH_RX_ORUN (1<<2) /* Receive overrun occurred */
+#define XZYNQETH_RX_DONE (1<<1) /* Frame successfully received */
+#define XZYNQETH_RX_BUF_USED (1<<0) /* Receive buffer used bit read */
+
+#define XZYNQETH_IRQ_PCS_AN (1<<16) /* PCS autonegotiation complete */
+/* External interrupt pin triggered */
+#define XZYNQETH_IRQ_EXT_INT (1<<15)
+#define XZYNQETH_IRQ_PAUSE_TX (1<<14) /* Pause frame transmitted */
+#define XZYNQETH_IRQ_PAUSE_0 (1<<13) /* Pause time has reached zero */
+#define XZYNQETH_IRQ_PAUSE_RX (1<<12) /* Pause frame received */
+#define XZYNQETH_IRQ_HRESP (1<<11) /* hresp not ok */
+#define XZYNQETH_IRQ_RX_ORUN (1<<10) /* Receive overrun occurred */
+#define XZYNQETH_IRQ_PCS_LINK (1<<9) /* Status of PCS link changed */
+#define XZYNQETH_IRQ_TX_DONE (1<<7) /* Frame transmitted ok */
+/* Transmit err occurred or no buffers*/
+#define XZYNQETH_IRQ_TX_ERROR (1<<6)
+#define XZYNQETH_IRQ_RETRY_EXC (1<<5) /* Retry limit exceeded */
+#define XZYNQETH_IRQ_TX_URUN (1<<4) /* Transmit underrun occurred */
+#define XZYNQETH_IRQ_TX_USED (1<<3) /* Tx buffer used bit read */
+#define XZYNQETH_IRQ_RX_USED (1<<2) /* Rx buffer used bit read */
+#define XZYNQETH_IRQ_RX_DONE (1<<1) /* Frame received ok */
+/* PHY management operation complete */
+#define XZYNQETH_IRQ_MAN_DONE (1<<0)
+#define XZYNQETH_IRQ_ALL (0xFFFFFFFF)/* Everything! */
+
+#define XZYNQETH_TBQE_USED (1<<31) /* Used bit. */
+#define XZYNQETH_TBQE_WRAP (1<<30) /* Wrap bit */
+#define XZYNQETH_TBQE_RETRY_EXC (1<<29) /* Retry limit exceeded. */
+#define XZYNQETH_TBQE_URUN (1<<28) /* Transmit underrun occurred. */
+#define XZYNQETH_TBQE_BUF_EXH (1<<27) /* Buffers exhausted mid frame. */
+#define XZYNQETH_TBQE_LATE_COL (1<<26) /* Late collision. */
+#define XZYNQETH_TBQE_NO_CRC (1<<16) /* No CRC */
+#define XZYNQETH_TBQE_LAST_BUF (1<<15) /* Last buffer */
+#define XZYNQETH_TBQE_LEN_MASK (0x3FFF) /* Mask for length field */
+#define XZYNQETH_TX_MAX_LEN (0x3FFF) /* Maximum transmit length value */
+/* Dummy value to check for free buffer*/
+#define XZYNQETH_TBQE_DUMMY (0x8000BFFF)
+
+#define XZYNQETH_RBQE_BROADCAST (1<<31) /* Broadcast frame */
+#define XZYNQETH_RBQE_MULTICAST (1<<30) /* Multicast hashed frame */
+#define XZYNQETH_RBQE_UNICAST (1<<29) /* Unicast hashed frame */
+#define XZYNQETH_RBQE_EXT_ADDR (1<<28) /* External address match */
+#define XZYNQETH_RBQE_SPEC_MATCH (1<<27) /* Specific address matched */
+/* Pos for base of specific match */
+#define XZYNQETH_RBQE_SPEC_BASE (25)
+#define XZYNQETH_RBQE_SPEC_MAT1 (1<<(RBQE_SPEC_BASE + 1))
+#define XZYNQETH_RBQE_SPEC_MAT0 (1<<RBQE_SPEC_BASE)
+#define XZYNQETH_RBQE_TYPE_MATCH (1<<24) /* Type ID matched */
+/* Position for base of type id match */
+#define XZYNQETH_RBQE_TYPE_BASE (22)
+#define XZYNQETH_RBQE_TYPE_MAT1 (1<<(RBQE_TYPE_BASE + 1))
+#define XZYNQETH_RBQE_TYPE_MAT0 (1<<RBQE_TYPE_BASE)
+#define XZYNQETH_RBQE_VLAN (1<<21) /* VLAN tagged */
+#define XZYNQETH_RBQE_PRIORITY (1<<20) /* Priority tagged */
+/* Position for base of VLAN priority */
+#define XZYNQETH_RBQE_VLAN_BASE (17)
+#define XZYNQETH_RBQE_VLAN_P2 (1<<(RBQE_VLAN_BASE+2))
+#define XZYNQETH_RBQE_VLAN_P1 (1<<(RBQE_VLAN_BASE+1))
+#define XZYNQETH_RBQE_VLAN_P0 (1<<RBQE_VLAN_BASE)
+#define XZYNQETH_RBQE_CFI (1<<16) /* CFI frame */
+#define XZYNQETH_RBQE_EOF (1<<15) /* End of frame. */
+#define XZYNQETH_RBQE_SOF (1<<14) /* Start of frame. */
+#define XZYNQETH_RBQE_LEN_MASK (0x3FFF) /* Mask for the length field. */
+#define XZYNQETH_RBQE_WRAP (1<<1) /* Wrap bit.. */
+#define XZYNQETH_RBQE_USED (1<<0) /* Used bit.. */
+#define XZYNQETH_RBQE_ADD_MASK (0xFFFFFFFC)/* Mask for address */
+
+#define XZYNQETH_REV_ID_MODEL_MASK (0x000F0000) /* Model ID */
+#define XZYNQETH_REV_ID_MODEL_BASE (16) /* For Shifting */
+#define XZYNQETH_REV_ID_REG_MODEL (0x00020000) /* GEM module ID */
+#define XZYNQETH_REV_ID_REV_MASK (0x0000FFFF) /* Revision ID */
+
+#define XZYNQETH_NET_CONTROL (0x00)
+#define XZYNQETH_NET_CONFIG (0x04)
+#define XZYNQETH_NET_STATUS (0x08)
+#define XZYNQETH_USER_IO (0x0C)
+#define XZYNQETH_TX_STATUS (0x14)
+#define XZYNQETH_RX_QPTR (0x18)
+#define XZYNQETH_TX_QPTR (0x1C)
+#define XZYNQETH_RX_STATUS (0x20)
+#define XZYNQETH_IRQ_STATUS (0x24)
+#define XZYNQETH_IRQ_ENABLE (0x28)
+#define XZYNQETH_IRQ_DISABLE (0x2C)
+#define XZYNQETH_IRQ_MASK (0x30)
+#define XZYNQETH_PHY_MAN (0x34)
+#define XZYNQETH_RX_PAUSE_TIME (0x38)
+#define XZYNQETH_TX_PAUSE_QUANT (0x3C)
+
+#define XZYNQETH_HASH_BOT (0x80)
+#define XZYNQETH_HASH_TOP (0x84)
+#define XZYNQETH_LADDR1_BOT (0x88)
+#define XZYNQETH_LADDR1_TOP (0x8C)
+#define XZYNQETH_LADDR2_BOT (0x90)
+#define XZYNQETH_LADDR2_TOP (0x94)
+#define XZYNQETH_LADDR3_BOT (0x98)
+#define XZYNQETH_LADDR3_TOP (0x9C)
+#define XZYNQETH_LADDR4_BOT (0xA0)
+#define XZYNQETH_LADDR4_TOP (0xA4)
+#define XZYNQETH_ID_CHECK1 (0xA8)
+#define XZYNQETH_ID_CHECK2 (0xAC)
+#define XZYNQETH_ID_CHECK3 (0xB0)
+#define XZYNQETH_ID_CHECK4 (0xB4)
+#define XZYNQETH_REV_ID (0xFC)
+
+#define XZYNQETH_OCT_TX_BOT (0x100)
+#define XZYNQETH_OCT_TX_TOP (0x104)
+#define XZYNQETH_STATS_FRAMES_TX (0x108)
+#define XZYNQETH_BROADCAST_TX (0x10C)
+#define XZYNQETH_MULTICAST_TX (0x110)
+#define XZYNQETH_STATS_PAUSE_TX (0x114)
+#define XZYNQETH_FRAME64_TX (0x118)
+#define XZYNQETH_FRAME65_TX (0x11C)
+#define XZYNQETH_FRAME128_TX (0x120)
+#define XZYNQETH_FRAME256_TX (0x124)
+#define XZYNQETH_FRAME512_TX (0x128)
+#define XZYNQETH_FRAME1024_TX (0x12C)
+#define XZYNQETH_FRAME1519_TX (0x130)
+#define XZYNQETH_STATS_TX_URUN (0x134)
+#define XZYNQETH_STATS_SINGLE_COL (0x138)
+#define XZYNQETH_STATS_MULTI_COL (0x13C)
+#define XZYNQETH_STATS_EXCESS_COL (0x140)
+#define XZYNQETH_STATS_LATE_COL (0x144)
+#define XZYNQETH_STATS_DEF_TX (0x148)
+#define XZYNQETH_STATS_CRS_ERRORS (0x14C)
+#define XZYNQETH_OCT_RX_BOT (0x150)
+#define XZYNQETH_OCT_RX_TOP (0x154)
+#define XZYNQETH_STATS_FRAMES_RX (0x158)
+#define XZYNQETH_BROADCAST_RX (0x15C)
+#define XZYNQETH_MULTICAST_RX (0x160)
+#define XZYNQETH_STATS_PAUSE_RX (0x164)
+#define XZYNQETH_FRAME64_RX (0x168)
+#define XZYNQETH_FRAME65_RX (0x16C)
+#define XZYNQETH_FRAME128_RX (0x170)
+#define XZYNQETH_FRAME256_RX (0x174)
+#define XZYNQETH_FRAME512_RX (0x178)
+#define XZYNQETH_FRAME1024_RX (0x17C)
+#define XZYNQETH_FRAME1519_RX (0x180)
+#define XZYNQETH_STATS_USIZE_FRAMES (0x184)
+#define XZYNQETH_STATS_EXCESS_LEN (0x188)
+#define XZYNQETH_STATS_JABBERS (0x18C)
+#define XZYNQETH_STATS_FCS_ERRORS (0x190)
+#define XZYNQETH_STATS_LENGTH_ERRORS (0x194)
+#define XZYNQETH_STATS_RX_SYM_ERR (0x198)
+#define XZYNQETH_STATS_ALIGN_ERRORS (0x19C)
+#define XZYNQETH_STATS_RX_RES_ERR (0x1a0)
+#define XZYNQETH_STATS_RX_ORUN (0x1a4)
+
+#define XZYNQETH_REG_TOP (0x23C)
#define gem_get_tbq_end(mac) ((mac)->tbq_end)
#define gem_get_tbq_current(mac) ((mac)->tbq_current)
* as of svn rev 1377.
*/
-#ifndef __XILINX_DF_UART_H__
-#define __XILINX_DF_UART_H__
+#ifndef __XILINX_ZYNQ_UART_H__
+#define __XILINX_ZYNQ_UART_H__
#include <asm/io.h>
#if defined(CONFIG_UART0)
# define UART_ID 0
# define UART_BASE XPSS_UART0_BASEADDR
-# define XDFUART_MASTER XPAR_XUARTPSS_0_CLOCK_HZ
+# define XZYNQUART_MASTER XPAR_XUARTPSS_0_CLOCK_HZ
#elif defined(CONFIG_UART1)
# define UART_ID 1
# define UART_BASE XPSS_UART1_BASEADDR
-# define XDFUART_MASTER XPAR_XUARTPSS_1_CLOCK_HZ
+# define XZYNQUART_MASTER XPAR_XUARTPSS_1_CLOCK_HZ
#else
# error "Need to configure a UART (0 or 1)"
#endif
/* UART register offsets */
-#define XDFUART_CR_OFFSET 0x00 /* Control Register [8:0] */
-#define XDFUART_MR_OFFSET 0x04 /* Mode Register [10:0] */
-#define XDFUART_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
-#define XDFUART_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
-#define XDFUART_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
-#define XDFUART_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
-#define XDFUART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
-#define XDFUART_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
-#define XDFUART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
-#define XDFUART_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
-#define XDFUART_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
-#define XDFUART_SR_OFFSET 0x2C /* Channel Status [11:0] */
-#define XDFUART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
-#define XDFUART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
-#define XDFUART_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
+#define XZYNQUART_CR_OFFSET 0x00 /* Control Register [8:0] */
+#define XZYNQUART_MR_OFFSET 0x04 /* Mode Register [10:0] */
+#define XZYNQUART_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
+#define XZYNQUART_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
+#define XZYNQUART_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
+#define XZYNQUART_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
+#define XZYNQUART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
+#define XZYNQUART_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
+#define XZYNQUART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
+#define XZYNQUART_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
+#define XZYNQUART_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
+#define XZYNQUART_SR_OFFSET 0x2C /* Channel Status [11:0] */
+#define XZYNQUART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
+#define XZYNQUART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
+#define XZYNQUART_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
/* Control register bits */
-#define XDFUART_CR_STOPBRK 0x00000100 /* Stop transmission of break */
-#define XDFUART_CR_STARTBRK 0x00000080 /* Set break */
-#define XDFUART_CR_TORST 0x00000040 /* RX timeout counter restart */
-#define XDFUART_CR_TX_DIS 0x00000020 /* TX disabled. */
-#define XDFUART_CR_TX_EN 0x00000010 /* TX enabled */
-#define XDFUART_CR_RX_DIS 0x00000008 /* RX disabled. */
-#define XDFUART_CR_RX_EN 0x00000004 /* RX enabled */
-#define XDFUART_CR_EN_DIS_MASK 0x0000003C /* Enable/disable Mask */
-#define XDFUART_CR_TXRST 0x00000002 /* TX logic reset */
-#define XDFUART_CR_RXRST 0x00000001 /* RX logic reset */
+#define XZYNQUART_CR_STOPBRK 0x00000100 /* Stop transmission of break */
+#define XZYNQUART_CR_STARTBRK 0x00000080 /* Set break */
+#define XZYNQUART_CR_TORST 0x00000040 /* RX timeout counter restart */
+#define XZYNQUART_CR_TX_DIS 0x00000020 /* TX disabled. */
+#define XZYNQUART_CR_TX_EN 0x00000010 /* TX enabled */
+#define XZYNQUART_CR_RX_DIS 0x00000008 /* RX disabled. */
+#define XZYNQUART_CR_RX_EN 0x00000004 /* RX enabled */
+#define XZYNQUART_CR_EN_DIS_MASK 0x0000003C /* Enable/disable Mask */
+#define XZYNQUART_CR_TXRST 0x00000002 /* TX logic reset */
+#define XZYNQUART_CR_RXRST 0x00000001 /* RX logic reset */
/* Mode register bits */
-#define XDFUART_MR_CCLK 0x00000400 /* Input clock selection */
-#define XDFUART_MR_CHMODE_R_LOOP 0x00000300 /* Remote loopback mode */
-#define XDFUART_MR_CHMODE_L_LOOP 0x00000200 /* Local loopback mode */
-#define XDFUART_MR_CHMODE_ECHO 0x00000100 /* Auto echo mode */
-#define XDFUART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
-#define XDFUART_MR_CHMODE_SHIFT 8 /* Mode shift */
-#define XDFUART_MR_CHMODE_MASK 0x00000300 /* Mode mask */
-#define XDFUART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
-#define XDFUART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */
-#define XDFUART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
-#define XDFUART_MR_STOPMODE_SHIFT 6 /* Stop bits setting shift */
-#define XDFUART_MR_STOPMODE_MASK 0x000000A0 /* Stop bits setting mask */
-#define XDFUART_MR_PARITY_NONE 0x00000020 /* No parity mode */
-#define XDFUART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
-#define XDFUART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
-#define XDFUART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
-#define XDFUART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
-#define XDFUART_MR_PARITY_SHIFT 3 /* Parity setting shift */
-#define XDFUART_MR_PARITY_MASK 0x00000038 /* Parity mask */
-#define XDFUART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
-#define XDFUART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
-#define XDFUART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
-#define XDFUART_MR_CHARLEN_SHIFT 1 /* data Length setting shift */
-#define XDFUART_MR_CHARLEN_MASK 0x00000006 /* Data length mask. */
-#define XDFUART_MR_CLKSEL 0x00000001 /* Input clock selection */
+#define XZYNQUART_MR_CCLK 0x00000400 /* Input clock selection */
+#define XZYNQUART_MR_CHMODE_R_LOOP 0x00000300 /* Remote loopback mode */
+#define XZYNQUART_MR_CHMODE_L_LOOP 0x00000200 /* Local loopback mode */
+#define XZYNQUART_MR_CHMODE_ECHO 0x00000100 /* Auto echo mode */
+#define XZYNQUART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
+#define XZYNQUART_MR_CHMODE_SHIFT 8 /* Mode shift */
+#define XZYNQUART_MR_CHMODE_MASK 0x00000300 /* Mode mask */
+#define XZYNQUART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
+#define XZYNQUART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */
+#define XZYNQUART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
+#define XZYNQUART_MR_STOPMODE_SHIFT 6 /* Stop bits setting shift */
+#define XZYNQUART_MR_STOPMODE_MASK 0x000000A0 /* Stop bits setting mask */
+#define XZYNQUART_MR_PARITY_NONE 0x00000020 /* No parity mode */
+#define XZYNQUART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
+#define XZYNQUART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
+#define XZYNQUART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
+#define XZYNQUART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
+#define XZYNQUART_MR_PARITY_SHIFT 3 /* Parity setting shift */
+#define XZYNQUART_MR_PARITY_MASK 0x00000038 /* Parity mask */
+#define XZYNQUART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
+#define XZYNQUART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
+#define XZYNQUART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
+/* data Length setting shift */
+#define XZYNQUART_MR_CHARLEN_SHIFT 1
+#define XZYNQUART_MR_CHARLEN_MASK 0x00000006 /* Data length mask. */
+#define XZYNQUART_MR_CLKSEL 0x00000001 /* Input clock selection */
/*
*
* All four registers have the same bit definitions.
*/
-#define XDFUART_IXR_DMS 0x00000200 /* Modem status change interrupt */
-#define XDFUART_IXR_TOUT 0x00000100 /* Timeout error interrupt */
-#define XDFUART_IXR_PARITY 0x00000080 /* Parity error interrupt */
-#define XDFUART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
-#define XDFUART_IXR_OVER 0x00000020 /* Overrun error interrupt */
-#define XDFUART_IXR_TXFULL 0x00000010 /* TX FIFO full interrupt. */
-#define XDFUART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt. */
-#define XDFUART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
-#define XDFUART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
-#define XDFUART_IXR_RXOVR 0x00000001 /* RX FIFO trigger interrupt. */
-#define XDFUART_IXR_MASK 0x000003FF /* Valid bit mask */
+/* Modem status change interrupt */
+#define XZYNQUART_IXR_DMS 0x00000200
+#define XZYNQUART_IXR_TOUT 0x00000100 /* Timeout error interrupt */
+#define XZYNQUART_IXR_PARITY 0x00000080 /* Parity error interrupt */
+#define XZYNQUART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
+#define XZYNQUART_IXR_OVER 0x00000020 /* Overrun error interrupt */
+#define XZYNQUART_IXR_TXFULL 0x00000010 /* TX FIFO full interrupt. */
+#define XZYNQUART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt. */
+#define XZYNQUART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
+#define XZYNQUART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
+#define XZYNQUART_IXR_RXOVR 0x00000001 /* RX FIFO trigger interrupt. */
+#define XZYNQUART_IXR_MASK 0x000003FF /* Valid bit mask */
/* Baud rate generator register
* Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
* in the MR register.
*/
-#define XDFUART_BAUDGEN_DISABLE 0x00000000 /* Disable clock */
-#define XDFUART_BAUDGEN_MASK 0x0000FFFF /* Valid bits mask */
+#define XZYNQUART_BAUDGEN_DISABLE 0x00000000 /* Disable clock */
+#define XZYNQUART_BAUDGEN_MASK 0x0000FFFF /* Valid bits mask */
/* Baud divisor rate register
*
* Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
* the MR_CCLK bit in the MR register.
*/
-#define XDFUART_BAUDDIV_MASK 0x000000FF /* 8 bit baud divider mask */
+#define XZYNQUART_BAUDDIV_MASK 0x000000FF /* 8 bit baud divider mask */
/* Receiver timeout register
* the receiver data line.
*
*/
-#define XDFUART_RXTOUT_DISABLE 0x00000000 /* Disable time out */
-#define XDFUART_RXTOUT_MASK 0x000000FF /* Valid bits mask */
+#define XZYNQUART_RXTOUT_DISABLE 0x00000000 /* Disable time out */
+#define XZYNQUART_RXTOUT_MASK 0x000000FF /* Valid bits mask */
/* Receiver fifo trigger level register
*
* Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
* which the RX FIFO triggers an interrupt event.
*/
-#define XDFUART_RXWM_DISABLE 0x00000000 /* Disable RX trigger interrupt */
-#define XDFUART_RXWM_MASK 0x0000001F /* Valid bits mask */
+#define XZYNQUART_RXWM_DISABLE 0x00000000 /* Disable RX trigger interrupt */
+#define XZYNQUART_RXWM_MASK 0x0000001F /* Valid bits mask */
/* Modem control register
*
* or a peripheral device emulating a modem.
*
*/
-#define XDFUART_MODEMCR_FCM 0x00000010 /* Flow control mode */
-#define XDFUART_MODEMCR_RTS 0x00000002 /* Request to send */
-#define XDFUART_MODEMCR_DTR 0x00000001 /* Data terminal ready */
+#define XZYNQUART_MODEMCR_FCM 0x00000010 /* Flow control mode */
+#define XZYNQUART_MODEMCR_RTS 0x00000002 /* Request to send */
+#define XZYNQUART_MODEMCR_DTR 0x00000001 /* Data terminal ready */
/* Modem status register
*
* register.
*
*/
-#define XDFUART_MODEMSR_FCMS 0x00000100 /* Flow control mode (FCMS) */
-#define XDFUART_MODEMSR_DCD 0x00000080 /* Complement of DCD input */
-#define XDFUART_MODEMSR_RI 0x00000040 /* Complement of RI input */
-#define XDFUART_MODEMSR_DSR 0x00000020 /* Complement of DSR input */
-#define XDFUART_MODEMSR_CTS 0x00000010 /* Complement of CTS input */
-#define XDFUART_MEDEMSR_DCDX 0x00000008 /* Delta DCD indicator */
-#define XDFUART_MEDEMSR_RIX 0x00000004 /* Change of RI */
-#define XDFUART_MEDEMSR_DSRX 0x00000002 /* Change of DSR */
-#define XDFUART_MEDEMSR_CTSX 0x00000001 /* Change of CTS */
+#define XZYNQUART_MODEMSR_FCMS 0x00000100 /* Flow control mode (FCMS) */
+#define XZYNQUART_MODEMSR_DCD 0x00000080 /* Complement of DCD input */
+#define XZYNQUART_MODEMSR_RI 0x00000040 /* Complement of RI input */
+#define XZYNQUART_MODEMSR_DSR 0x00000020 /* Complement of DSR input */
+#define XZYNQUART_MODEMSR_CTS 0x00000010 /* Complement of CTS input */
+#define XZYNQUART_MEDEMSR_DCDX 0x00000008 /* Delta DCD indicator */
+#define XZYNQUART_MEDEMSR_RIX 0x00000004 /* Change of RI */
+#define XZYNQUART_MEDEMSR_DSRX 0x00000002 /* Change of DSR */
+#define XZYNQUART_MEDEMSR_CTSX 0x00000001 /* Change of CTS */
/* Channel status register
*
* even if these are masked out by the interrupt mask register.
*
*/
-#define XDFUART_SR_FLOWDEL 0x00001000 /* RX FIFO fill over flow delay */
-#define XDFUART_SR_TACTIVE 0x00000800 /* TX active */
-#define XDFUART_SR_RACTIVE 0x00000400 /* RX active */
-#define XDFUART_SR_DMS 0x00000200 /* Delta modem status change */
-#define XDFUART_SR_TOUT 0x00000100 /* RX timeout */
-#define XDFUART_SR_PARITY 0x00000080 /* RX parity error */
-#define XDFUART_SR_FRAME 0x00000040 /* RX frame error */
-#define XDFUART_SR_OVER 0x00000020 /* RX overflow error */
-#define XDFUART_SR_TXFULL 0x00000010 /* TX FIFO full */
-#define XDFUART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
-#define XDFUART_SR_RXFULL 0x00000004 /* RX FIFO full */
-#define XDFUART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
-#define XDFUART_SR_RXOVR 0x00000001 /* RX FIFO fill over trigger */
+/* RX FIFO fill over flow delay */
+#define XZYNQUART_SR_FLOWDEL 0x00001000
+#define XZYNQUART_SR_TACTIVE 0x00000800 /* TX active */
+#define XZYNQUART_SR_RACTIVE 0x00000400 /* RX active */
+#define XZYNQUART_SR_DMS 0x00000200 /* Delta modem status change */
+#define XZYNQUART_SR_TOUT 0x00000100 /* RX timeout */
+#define XZYNQUART_SR_PARITY 0x00000080 /* RX parity error */
+#define XZYNQUART_SR_FRAME 0x00000040 /* RX frame error */
+#define XZYNQUART_SR_OVER 0x00000020 /* RX overflow error */
+#define XZYNQUART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define XZYNQUART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
+#define XZYNQUART_SR_RXFULL 0x00000004 /* RX FIFO full */
+#define XZYNQUART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
+#define XZYNQUART_SR_RXOVR 0x00000001 /* RX FIFO fill over trigger */
/* Flow delay register
*
* level of the flow delay trigger and the flow delay trigger is not activated.
* A value less than 4 disables the flow delay.
*/
-#define XDFUART_FLOWDEL_MASK XDFUART_RXWM_MASK /* Valid bit mask */
+#define XZYNQUART_FLOWDEL_MASK XZYNQUART_RXWM_MASK /* Valid bit mask */
/* Some access macros */
#define xdfuart_readl(reg) \
- readl((void*)UART_BASE + XDFUART_##reg##_OFFSET)
+ readl((void *)UART_BASE + XZYNQUART_##reg##_OFFSET)
#define xdfuart_writel(reg,value) \
- writel((value),(void*)UART_BASE + XDFUART_##reg##_OFFSET)
+ writel((value), (void *)UART_BASE + XZYNQUART_##reg##_OFFSET)
-#endif /* __XILINX_DF_UART_H__ */
+#endif /* __XILINX_ZYNQ_UART_H__ */
projects / thirdparty / u-boot.git / commitdiff
