phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage

Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES
wrapper driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig
index 111085f235dc5f92bbbd0c24c8ecf8f36cad532d..df750b26d66bc194c50d3605e3b7c96bc0dee34e 100644 (file)
--- a/drivers/phy/ti/Kconfig
+++ b/drivers/phy/ti/Kconfig
@@ -7,3 +7,13 @@ config PHY_J721E_WIZ
          signals to the SERDES (Sierra/Torrent). This driver configures
          three clock selects (pll0, pll1, dig) and resets for each of the
          lanes.
+
+config SPL_PHY_J721E_WIZ
+       bool "TI J721E WIZ (SERDES Wrapper) support"
+       depends on ARCH_K3
+       help
+         This option enables support for WIZ module present in TI's J721E
+         SoC at SPL stage. WIZ is a serdes wrapper used to configure some
+         of the input signals to the SERDES (Sierra/Torrent). This driver
+         configures three clock selects (pll0, pll1, dig) and resets for
+         each of the lanes.