(set_attr "amdfam10_decode" "double,double")
(set_attr "bdver1_decode" "double,double")])
+(define_insn "*fix_trunc<mode>si_sse_2_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI
+ (subreg:SI
+ (fix:DI (match_operand:MODEF 1 "nonimmediate_operand" "v,m")) 0)))]
+ "TARGET_64BIT
+ && SSE_FLOAT_MODE_P (<MODE>mode)
+ && (!TARGET_FISTTP || TARGET_SSE_MATH)"
+ "%vcvtt<ssemodesuffix>2si{l}\t{%1, %k0|%k0, %1}"
+ [(set_attr "type" "sseicvt")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "prefix_rex" "*")
+ (set_attr "mode" "<MODE>")
+ (set_attr "athlon_decode" "double,vector")
+ (set_attr "amdfam10_decode" "double,double")
+ (set_attr "bdver1_decode" "double,double")])
+
;; Avoid vector decoded forms of the instruction.
(define_peephole2
[(match_scratch:MODEF 2 "x")