arm64: dts: freescale: imx93-phycore-som: Delay the phy reset by a gpio

According to the datasheet the phy needs to be held in reset until the
reference clock got stable. Even though no issue was observed, fix this
as the software should always comply with the specification.

Use gpio4 23, which is connected to the phy reset pin. On the same pin
RX_ER was used before, but this signal is optional and can be dropped.

Note: This comes into effect with the phyCOREs SOM hardware revision 4.
In revisions before, this gpio is not connected, and the phy reset is
managed with the global hardware reset circuit.

Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index c6f5aa38ebf99b43adfb8bfd23f3859fcdb0fc8e..89552ae706602d35eb237dece8280dd2bd9ff501 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -85,6 +85,8 @@
                ethphy1: ethernet-phy@1 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <1>;
+                       reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
+                       reset-assert-us = <30>;
                };
        };
 };
@@ -206,14 +208,17 @@
                fsl,pins = <
                        MX93_PAD_ENET2_MDC__ENET1_MDC                   0x50e
                        MX93_PAD_ENET2_MDIO__ENET1_MDIO                 0x502
-                       MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0             0x57e
-                       MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1             0x57e
-                       MX93_PAD_ENET2_RXC__ENET1_RX_ER                 0x5fe
+                       /* the three pins below are connected to PHYs straps,
+                        * that is what the pull-up/down setting is for.
+                        */
+                       MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0             0x37e
+                       MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1             0x37e
                        MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL       0x57e
                        MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0             0x50e
                        MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1             0x50e
                        MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL       0x50e
                        MX93_PAD_ENET2_TD2__ENET1_TX_CLK                0x4000050e
+                       MX93_PAD_ENET2_RXC__GPIO4_IO23                  0x51e
                >;
        };