drm/sun4i: layers: Make regmap for layers configurable

Till DE33, there were no reason to decouple registers from mixer.
However, with future new plane driver, this will be necessary.

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Tested-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20251104180942.61538-21-jernej.skrabec@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 6cd91595abf2dcda87162fbc998073cfcc3af0e4..f8af959e5d66d0608bd357fe1ef08488770c539d 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -332,7 +332,9 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
                else
                        type = DRM_PLANE_TYPE_OVERLAY;
 
-               layer = sun8i_vi_layer_init_one(drm, mixer, type, i, plane_cnt);
+               layer = sun8i_vi_layer_init_one(drm, mixer, type,
+                                               mixer->engine.regs, i,
+                                               plane_cnt);
                if (IS_ERR(layer)) {
                        dev_err(drm->dev,
                                "Couldn't initialize overlay plane\n");
@@ -351,7 +353,8 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
                else
                        type = DRM_PLANE_TYPE_OVERLAY;
 
-               layer = sun8i_ui_layer_init_one(drm, mixer, type, index,
+               layer = sun8i_ui_layer_init_one(drm, mixer, type,
+                                               mixer->engine.regs, index,
                                                plane_cnt);
                if (IS_ERR(layer)) {
                        dev_err(drm->dev, "Couldn't initialize %s plane\n",

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index b5badfa2c997e81b0cfd0a47d60e3f685fd66c6d..2e3689008b506cd377ff589e74bbec458c5c0d20 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -214,6 +214,7 @@ struct sun8i_layer {
        int                     type;
        int                     channel;
        int                     overlay;
+       struct regmap           *regs;
 };
 
 static inline struct sun8i_layer *

diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
index 5651a6290f98ec862a3bbdec493f2bd5c2444a1b..a038c170680392a2bae1342c77bc29a30f2399fd 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
@@ -54,7 +54,7 @@ static void sun8i_ui_layer_update_attributes(struct sun8i_layer *layer,
        val |= hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
        val |= SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
 
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay), val);
 }
 
@@ -88,10 +88,10 @@ static void sun8i_ui_layer_update_coord(struct sun8i_layer *layer,
        DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
                         state->src.x1 >> 16, state->src.y1 >> 16);
        DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, layer->overlay),
                     insize);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base),
                     insize);
 
@@ -150,13 +150,13 @@ static void sun8i_ui_layer_update_buffer(struct sun8i_layer *layer,
 
        /* Set the line width */
        DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, layer->overlay),
                     fb->pitches[0]);
 
        DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &dma_addr);
 
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, layer->overlay),
                     lower_32_bits(dma_addr));
 }
@@ -264,6 +264,7 @@ static const uint64_t sun8i_layer_modifiers[] = {
 struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
                                            struct sun8i_mixer *mixer,
                                            enum drm_plane_type type,
+                                           struct regmap *regs,
                                            int index,
                                            int plane_cnt)
 {
@@ -278,6 +279,7 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
        layer->type = SUN8I_LAYER_TYPE_UI;
        layer->channel = index;
        layer->overlay = 0;
+       layer->regs = regs;
 
        /* possible crtcs are set later */
        ret = drm_universal_plane_init(drm, &layer->plane, 0,

diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
index 0613b34d36e0d31a079ccc85e3aaba705556b54b..e0b2cfa02749167b3fea35569b56a6ffb18cfdd0 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
@@ -52,6 +52,7 @@ struct sun8i_layer;
 struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
                                            struct sun8i_mixer *mixer,
                                            enum drm_plane_type type,
+                                           struct regmap *regs,
                                            int index,
                                            int plane_cnt);
 #endif /* _SUN8I_UI_LAYER_H_ */

diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
index fcd72c4fd49a9ee3322cb3c7a57146c25ede3677..2fc54dc2030769dbd89483692fb50c300b189778 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
@@ -143,7 +143,7 @@ void sun8i_ui_scaler_enable(struct sun8i_layer *layer, bool enable)
        else
                val = 0;
 
-       regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val);
+       regmap_write(layer->regs, SUN8I_SCALER_GSU_CTRL(base), val);
 }
 
 void sun8i_ui_scaler_setup(struct sun8i_layer *layer,
@@ -168,22 +168,22 @@ void sun8i_ui_scaler_setup(struct sun8i_layer *layer,
        insize = SUN8I_UI_SCALER_SIZE(src_w, src_h);
        outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h);
 
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_GSU_OUTSIZE(base), outsize);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_GSU_INSIZE(base), insize);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_GSU_HSTEP(base), hscale);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_GSU_VSTEP(base), vscale);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_GSU_HPHASE(base), hphase);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_GSU_VPHASE(base), vphase);
        offset = sun8i_ui_scaler_coef_index(hscale) *
                        SUN8I_UI_SCALER_COEFF_COUNT;
        for (i = 0; i < SUN8I_UI_SCALER_COEFF_COUNT; i++)
-               regmap_write(mixer->engine.regs,
+               regmap_write(layer->regs,
                             SUN8I_SCALER_GSU_HCOEFF(base, i),
                             lan2coefftab16[offset + i]);
 }

diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index dd24f9eee685d5e06f0ac2d7dbf2189f1c580b7b..3e414d7fe236d55ec3a99e6b233ee58910cd4428 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -50,12 +50,12 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer,
                        SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL :
                        SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED;
        } else if (mixer->cfg->vi_num == 1) {
-               regmap_write(mixer->engine.regs,
+               regmap_write(layer->regs,
                             SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG,
                             SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8));
        }
 
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val);
 }
 
@@ -113,10 +113,10 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
                         (state->src.x1 >> 16) & ~(format->hsub - 1),
                         (state->src.y1 >> 16) & ~(format->vsub - 1));
        DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, layer->overlay),
                     insize);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base),
                     insize);
 
@@ -171,19 +171,19 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
                sun8i_vi_scaler_enable(layer, false);
        }
 
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base),
                     SUN8I_MIXER_CHAN_VI_DS_N(hn) |
                     SUN8I_MIXER_CHAN_VI_DS_M(hm));
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base),
                     SUN8I_MIXER_CHAN_VI_DS_N(hn) |
                     SUN8I_MIXER_CHAN_VI_DS_M(hm));
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base),
                     SUN8I_MIXER_CHAN_VI_DS_N(vn) |
                     SUN8I_MIXER_CHAN_VI_DS_M(vm));
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base),
                     SUN8I_MIXER_CHAN_VI_DS_N(vn) |
                     SUN8I_MIXER_CHAN_VI_DS_M(vm));
@@ -232,7 +232,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer,
                /* Set the line width */
                DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
                                 i + 1, fb->pitches[i]);
-               regmap_write(mixer->engine.regs,
+               regmap_write(layer->regs,
                             SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base,
                                                             layer->overlay, i),
                             fb->pitches[i]);
@@ -240,7 +240,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer,
                DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
                                 i + 1, &dma_addr);
 
-               regmap_write(mixer->engine.regs,
+               regmap_write(layer->regs,
                             SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
                                                                 layer->overlay, i),
                             lower_32_bits(dma_addr));
@@ -410,6 +410,7 @@ static const uint64_t sun8i_layer_modifiers[] = {
 struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
                                            struct sun8i_mixer *mixer,
                                            enum drm_plane_type type,
+                                           struct regmap *regs,
                                            int index,
                                            int plane_cnt)
 {
@@ -427,6 +428,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
        layer->type = SUN8I_LAYER_TYPE_VI;
        layer->channel = index;
        layer->overlay = 0;
+       layer->regs = regs;
 
        if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
                formats = sun8i_vi_layer_de3_formats;

diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
index a568e1db1e1955f45239cc0dc065a41076142bad..70766d752fa65d2bc974d421c1f97018b42b0896 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
@@ -57,6 +57,7 @@ struct sun8i_layer;
 struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
                                            struct sun8i_mixer *mixer,
                                            enum drm_plane_type type,
+                                           struct regmap *regs,
                                            int index,
                                            int plane_cnt);
 #endif /* _SUN8I_VI_LAYER_H_ */

diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
index a76677a1649f6b8e9baaee3953a0447fafdaffe5..0e308feb492ae503973e59586b74f99a556fa7bf 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
@@ -911,10 +911,9 @@ static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base,
 
 void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable)
 {
-       struct sun8i_mixer *mixer = layer->mixer;
        u32 val, base;
 
-       base = sun8i_vi_scaler_base(mixer, layer->channel);
+       base = sun8i_vi_scaler_base(layer->mixer, layer->channel);
 
        if (enable)
                val = SUN8I_SCALER_VSU_CTRL_EN |
@@ -922,7 +921,7 @@ void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable)
        else
                val = 0;
 
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_CTRL(base), val);
 }
 
@@ -968,36 +967,36 @@ void sun8i_vi_scaler_setup(struct sun8i_layer *layer,
                else
                        val = SUN50I_SCALER_VSU_SCALE_MODE_NORMAL;
 
-               regmap_write(mixer->engine.regs,
+               regmap_write(layer->regs,
                             SUN50I_SCALER_VSU_SCALE_MODE(base), val);
        }
 
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_OUTSIZE(base), outsize);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_YINSIZE(base), insize);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_YHSTEP(base), hscale);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_YVSTEP(base), vscale);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_YHPHASE(base), hphase);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_YVPHASE(base), vphase);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_CINSIZE(base),
                     SUN8I_VI_SCALER_SIZE(src_w / format->hsub,
                                          src_h / format->vsub));
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_CHSTEP(base),
                     hscale / format->hsub);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_CVSTEP(base),
                     vscale / format->vsub);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_CHPHASE(base), chphase);
-       regmap_write(mixer->engine.regs,
+       regmap_write(layer->regs,
                     SUN8I_SCALER_VSU_CVPHASE(base), cvphase);
-       sun8i_vi_scaler_set_coeff(mixer->engine.regs, base,
+       sun8i_vi_scaler_set_coeff(layer->regs, base,
                                  hscale, vscale, format);
 }