x86: Add target("80387") function attribute

Add target("80387") attribute to enable and disable x87 instructions in a
function.

gcc/

	PR target/121541
	* config/i386/i386-options.cc
	(ix86_valid_target_attribute_inner_p): Add target("80387")
	attribute.  Set the mask bit in opts_set->x_target_flags if the
	mask bit in opts->x_target_flags is updated.
	* doc/extend.texi: Document target("80387") function attribute.

gcc/testsuite/

	PR target/121541
	* gcc.target/i386/pr121541-1a.c: New test.
	* gcc.target/i386/pr121541-1b.c: Likewise.
	* gcc.target/i386/pr121541-2.c: Likewise.
	* gcc.target/i386/pr121541-3.c: Likewise.
	* gcc.target/i386/pr121541-4.c: Likewise.
	* gcc.target/i386/pr121541-5a.c: Likewise.
	* gcc.target/i386/pr121541-5b.c: Likewise.

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 136c0f2e9663ddfe612f472f1393b3ffcc456846..abb5dd7700e7f981566db32c4892c5a10475cff8 100644 (file)
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1172,6 +1172,10 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
                   OPT_mrecip,
                   MASK_RECIP),
 
+    IX86_ATTR_YES ("80387",
+                  OPT_m80387,
+                  MASK_80387),
+
     IX86_ATTR_IX86_YES ("general-regs-only",
                        OPT_mgeneral_regs_only,
                        OPTION_MASK_GENERAL_REGS_ONLY),
@@ -1281,6 +1285,8 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
 
       else if (type == ix86_opt_yes || type == ix86_opt_no)
        {
+         opts_set->x_target_flags |= mask;
+
          if (type == ix86_opt_no)
            opt_set_p = !opt_set_p;
 

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 3b9b4286f52922fb84ddea8e1eed375e15df50ec..cc9005439a492ff73d19801d76bfd1e23e9400e9 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -6798,6 +6798,11 @@ Enable/disable the generation of RCPSS, RCPPS, RSQRTSS and RSQRTPS
 instructions followed an additional Newton-Raphson step instead of
 doing a floating-point division.
 
+@cindex @code{target("80387")} function attribute, x86
+@item 80387
+@itemx no-80387
+Generate code containing 80387 instructions for floating point.
+
 @cindex @code{target("general-regs-only")} function attribute, x86
 @item general-regs-only
 Generate code which uses only the general registers.

diff --git a/gcc/testsuite/gcc.target/i386/pr121541-1a.c b/gcc/testsuite/gcc.target/i386/pr121541-1a.c
new file mode 100644 (file)
index 0000000..83884a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr121541-1a.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=x86-64" } */
+
+extern long double d;
+
+__attribute__ ((target("no-80387")))
+void
+func1 (void)
+{
+  d *= 3; /* { dg-error "x87 register return with x87 disabled" } */
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr121541-1b.c b/gcc/testsuite/gcc.target/i386/pr121541-1b.c
new file mode 100644 (file)
index 0000000..f440b14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr121541-1b.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2" } */
+
+#include "pr121541-1a.c"
+
+/* { dg-final { scan-assembler "call\[\\t \]+_?__mulxf3" } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr121541-2.c b/gcc/testsuite/gcc.target/i386/pr121541-2.c
new file mode 100644 (file)
index 0000000..281341e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr121541-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-80387" } */
+
+extern long double d;
+
+__attribute__ ((target("80387")))
+void
+func1 (void)
+{
+  d *= 3;
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr121541-3.c b/gcc/testsuite/gcc.target/i386/pr121541-3.c
new file mode 100644 (file)
index 0000000..380fab2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr121541-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mgeneral-regs-only" } */
+
+extern long double d;
+
+__attribute__ ((target("80387")))
+void
+func1 (void)
+{
+  d *= 3;
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr121541-4.c b/gcc/testsuite/gcc.target/i386/pr121541-4.c
new file mode 100644 (file)
index 0000000..1f4381a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr121541-4.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern long double d;
+
+__attribute__ ((target("general-regs-only","80387")))
+void
+func1 (void)
+{
+  d *= 3;
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr121541-5a.c b/gcc/testsuite/gcc.target/i386/pr121541-5a.c
new file mode 100644 (file)
index 0000000..e6137e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr121541-5a.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=x86-64" } */
+
+extern long double d;
+
+__attribute__ ((target("80387","general-regs-only")))
+void
+func1 (void)
+{
+  d *= 3; /* { dg-error "x87 register return with x87 disabled" } */
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr121541-5b.c b/gcc/testsuite/gcc.target/i386/pr121541-5b.c
new file mode 100644 (file)
index 0000000..b61a7fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr121541-5b.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2" } */
+
+#include "pr121541-5a.c"
+
+/* { dg-final { scan-assembler "call\[\\t \]+_?__mulxf3" } } */