arm64: zynqmp: Fix psu_init* external functions

In older vivado version some psu_init* files didn't contain prog_reg
function that's why it was added to xil_io.h.
The same with mask*() which were missing.

From some pre v2017.1 these issues were fixed that's why
some functions were commented in origin psu_init* files.

This patch adds prog_reg() and mask*() to psu_init* files
where it is missing and remove comment from files which have
prog_reg() already.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index eeff0ab3f8d264cc8e431854dbc4a8a2e477b138..679d234b0709310175af9ba30617409e7eee0514 100644 (file)
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -33,23 +33,9 @@ int Xil_In32(unsigned long addr)
        return readl(addr);
 }
 
-__weak void prog_reg(unsigned long addr, unsigned long mask,
-                    unsigned long shift, unsigned long value)
-{
-       int rdata = 0;
-
-       rdata = Xil_In32(addr);
-       rdata = rdata & (~mask);
-       rdata = rdata | (value << shift);
-       Xil_Out32(addr,rdata);
-}
-
-void mask_delay(u32 delay);
 void usleep(u32 sleep)
 {
        udelay(sleep);
 }
-int mask_poll(u32 add, u32 mask);
-int mask_pollOnValue(u32 add, u32 mask, u32 value);
 
 #endif /* XIL_IO_H */

diff --git a/board/xilinx/zynqmp/zynqmp-ep108/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-ep108/psu_init_gpl.c
index bb98c120f92cfdf3cd3b481bf659c1d3aec952ee..bad074fdc6be563e85e6a9f023be727d17d7584e 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-ep108/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-ep108/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+                    unsigned long shift, unsigned long value)
+{
+       int rdata = 0;
+
+       rdata = Xil_In32(addr);
+       rdata = rdata & (~mask);
+       rdata = rdata | (value << shift);
+       Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
index 99681d511444fb1c12a66309ea6ecb670b3ca255..e14c43b0623264ea724f1ce3875b623b2c1eefbb 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+                    unsigned long shift, unsigned long value)
+{
+       int rdata = 0;
+
+       rdata = Xil_In32(addr);
+       rdata = rdata & (~mask);
+       rdata = rdata | (value << shift);
+       Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
index ebd93d789bed8220161948c071eecf0537fedaa3..d0b0674c8166e7c01c8aaea3604ce26e69ae4f17 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+                    unsigned long shift, unsigned long value)
+{
+       int rdata = 0;
+
+       rdata = Xil_In32(addr);
+       rdata = rdata & (~mask);
+       rdata = rdata | (value << shift);
+       Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
index 6b3d75e9dc74eeaa93f5ebe7d93f9923b2ce5254..2f86cb14081b82e9143d75865896ce394326738f 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+                    unsigned long shift, unsigned long value)
+{
+       int rdata = 0;
+
+       rdata = Xil_In32(addr);
+       rdata = rdata & (~mask);
+       rdata = rdata | (value << shift);
+       Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
index e02361dbf1ad8ce5fb278983957f4ed8af389b5b..0827dd5f65ed62b3f62a664d1b8a7b64f94cd697 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+                    unsigned long shift, unsigned long value)
+{
+       int rdata = 0;
+
+       rdata = Xil_In32(addr);
+       rdata = rdata & (~mask);
+       rdata = rdata | (value << shift);
+       Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
index 85b31be046f89980952e5f22d70c73ef8a6784b9..0d3f0d667015e726bb2d067e8ef29963aea1323e 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+                    unsigned long shift, unsigned long value)
+{
+       int rdata = 0;
+
+       rdata = Xil_In32(addr);
+       rdata = rdata & (~mask);
+       rdata = rdata | (value << shift);
+       Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c
index d0546390560977196514e7d8d164dd5effd20cda..b84f819556b3accaeece9ebb939c80b3c1175db5 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c
@@ -38,7 +38,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        RegVal |= (val & mask);
        Xil_Out32 (offset, RegVal);
 }
-/*
+
        void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
            int rdata =0;
            rdata  = Xil_In32(addr);
@@ -46,7 +46,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
            rdata  = rdata | (value << shift);
            Xil_Out32(addr,rdata);
            }
-*/
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revB/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revB/psu_init_gpl.c
index 4760d957e238c87e36382883622a855ef578f5ff..d7e538998f6eb9f07c2eb76bd0ec66272748fd3d 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zcu100-revB/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu100-revB/psu_init_gpl.c
@@ -38,7 +38,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        RegVal |= (val & mask);
        Xil_Out32 (offset, RegVal);
 }
-/*
+
        void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
            int rdata =0;
            rdata  = Xil_In32(addr);
@@ -46,7 +46,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
            rdata  = rdata | (value << shift);
            Xil_Out32(addr,rdata);
            }
-*/
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c
index 6f6a516315eb171d9b73d1b9d6c6baa19a5405ab..4bc732f69e20d0a14e93c72408f8fe4bcaa08caa 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c
@@ -38,7 +38,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        RegVal |= (val & mask);
        Xil_Out32 (offset, RegVal);
 }
-/*
+
        void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
            int rdata =0;
            rdata  = Xil_In32(addr);
@@ -46,7 +46,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
            rdata  = rdata | (value << shift);
            Xil_Out32(addr,rdata);
            }
-*/
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>

diff --git a/board/xilinx/zynqmp/zynqmp-zcu106/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106/psu_init_gpl.c
index 2146fe005f4d2542d2a5e23216cf18f86149f16b..58da9584b8421653f587236325e5a96b01c06496 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zcu106/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu106/psu_init_gpl.c
@@ -38,7 +38,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
        RegVal |= (val & mask);
        Xil_Out32 (offset, RegVal);
 }
-/*
+
        void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
            int rdata =0;
            rdata  = Xil_In32(addr);
@@ -46,7 +46,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
            rdata  = rdata | (value << shift);
            Xil_Out32(addr,rdata);
            }
-*/
+
 unsigned long psu_pll_init_data() {
                // : RPLL INIT
                /*Register : RPLL_CFG @ 0XFF5E0034</p>