clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs

[ Upstream commit 5a33a64524e6381c399e5e42571d9363ffc0bed4 ]

The clk_alpha_pll_stromer_plus_set_rate() function does not
sets the ALPHA_EN bit in the USER_CTL register, so setting
rates which requires using alpha mode works only if the bit
gets set already prior calling the function.

Extend the function to set the ALPHA_EN bit in order to allow
using fractional rates regardless whether the bit gets set
previously or not.

Fixes: 84da48921a97 ("clk: qcom: clk-alpha-pll: introduce stromer plus ops")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240508-stromer-plus-alpha-en-v1-1-6639ce01ca5b@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index be18ff983d35ca72fba3d672a32243040abe16b1..003308a288968afda6b5b1a72f931a8a87973964 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -2555,6 +2555,9 @@ static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
        regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
                                        a >> ALPHA_BITWIDTH);
 
+       regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+                          PLL_ALPHA_EN, PLL_ALPHA_EN);
+
        regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
 
        /* Wait five micro seconds or more */