return sizeof(*gpu_metrics);
}
+static void smu_v15_0_8_get_unique_id(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ struct smu_table_context *smu_table = &smu->smu_table;
+ PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable;
+
+ adev->unique_id = pptable->PublicSerialNumberMID;
+}
+
static const struct pptable_funcs smu_v15_0_8_ppt_funcs = {
.init_allowed_features = smu_v15_0_8_init_allowed_features,
.set_default_dpm_table = smu_v15_0_8_set_default_dpm_table,
.mode2_reset = smu_v15_0_8_mode2_reset,
.get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq,
.get_gpu_metrics = smu_v15_0_8_get_gpu_metrics,
+ .get_unique_id = smu_v15_0_8_get_unique_id,
};
static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu,