drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy

Program sequence from port clock ctl except for the SSC
enablement part which will be taken care of later.

Bspec: 74492
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-6-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c92026fe7b8f143c6305e8376b35ecc8d6de3722..b111a893b4288849041c8cab8fd2db9bfe02bd77 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -43,6 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
                                     const struct intel_crtc_state *crtc_state);
 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
 void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
+bool intel_cx0_is_hdmi_frl(u32 clock);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index c65333cc9494fbafb90311471530908fa0dad83f..b6f71425cd195cfe9625654985fb05dfad857500 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -11,6 +11,7 @@
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
+#include "intel_hdmi.h"
 #include "intel_lt_phy.h"
 #include "intel_lt_phy_regs.h"
 #include "intel_tc.h"
@@ -108,13 +109,49 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
        intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
 }
 
+static void
+intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
+                                   const struct intel_crtc_state *crtc_state,
+                                   bool lane_reversal)
+{
+       struct intel_display *display = to_intel_display(encoder);
+       u32 val = 0;
+
+       intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
+                    XELPDP_PORT_REVERSAL,
+                    lane_reversal ? XELPDP_PORT_REVERSAL : 0);
+
+       val |= XELPDP_FORWARD_CLOCK_UNGATE;
+
+       /*
+        * We actually mean MACCLK here and not MAXPCLK when using LT Phy
+        * but since the register bits still remain the same we use
+        * the same definition
+        */
+       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+           intel_hdmi_is_frl(crtc_state->port_clock))
+               val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
+       else
+               val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
+
+       intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+                    XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
+                    XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
+                    XELPDP_SSC_ENABLE_PLLB, val);
+}
+
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
                             const struct intel_crtc_state *crtc_state)
 {
+       struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+       bool lane_reversal = dig_port->lane_reversal;
+
        /* 1. Enable MacCLK at default 162 MHz frequency. */
        intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
 
        /* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
+       intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
+
        /* 3. Change owned PHY lanes power to Ready state. */
        /*
         * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,