DP will use PS PLL to generate required clock.
Remove this dp_clk_hack.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
compatible = "mmc-pwrseq-simple";
reset-gpios = <&max3107 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */
};
-
- dp_clk_wiz: dp_clk_wiz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <267439000>;
- clock-accuracy = <0x64>;
- };
};
&dcc {
&xilinx_drm {
status = "okay";
- clocks = <&dp_clk_wiz>;
};
&xlnx_dp {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
};
-
- /* FIXME - not tested */
- dp_clk_wiz: dp_clk_wiz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <267439000>;
- clock-accuracy = <0x64>;
- };
};
&dcc {
&xilinx_drm {
status = "okay";
- clocks = <&dp_clk_wiz>;
};
&xlnx_dp {