+2011-08-27 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/sse.md (*absneg<mode>2): Fix split condition.
+ (vec_extract_lo_<mode>): Prevent both operands in memory.
+ (vec_extract_lo_v16hi): Ditto.
+ (*vec_extract_v4sf_mem): Add TARGET_SSE insn constraint.
+
+2011-08-27 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/sse.md (mulv16qi3): Attach REG_EQUAL note.
+ (*sse2_mulv4si3): Ditto.
+ (mulv2di3): Ditto.
+ * config/i386/i386.c (legitimize_tls_address): Change REG_EQIV
+ notes to REG_EQUAL.
+
2011-08-27 Uros Bizjak <ubizjak@gmail.com>
PR target/50202
* config/i386/sse.md (sse4_2_pcmpestr): Emit NOTE_INSN_DELETED note
when all outputs are unused.
- (sse4_2_pcmpestr): Ditto.
+ (sse4_2_pcmpistr): Ditto.
2011-08-26 Uros Bizjak <ubizjak@gmail.com>
tp = get_thread_pointer (true);
dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
- set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
+ set_unique_reg_note (get_last_insn (), REG_EQUAL, x);
}
else
{
emit_insn (gen_tls_dynamic_gnu2_32 (base, tmp, pic));
tp = get_thread_pointer (true);
- set_unique_reg_note (get_last_insn (), REG_EQUIV,
+ set_unique_reg_note (get_last_insn (), REG_EQUAL,
gen_rtx_MINUS (Pmode, tmp, tp));
}
else
insns = get_insns ();
end_sequence ();
- /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
+ /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
share the LD_BASE result with other LD model accesses. */
eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
UNSPEC_TLS_LD_BASE);
{
dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
- set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
+ set_unique_reg_note (get_last_insn (), REG_EQUAL, x);
}
break;
(use (match_operand:VF 2 "nonimmediate_operand" "xm,0, xm,x"))]
"TARGET_SSE"
"#"
- "reload_completed"
+ "&& reload_completed"
[(const_int 0)]
{
enum rtx_code absneg_op;
(vec_select:<ssehalfvecmode>
(match_operand:VI8F_256 1 "nonimmediate_operand" "xm,x")
(parallel [(const_int 0) (const_int 1)])))]
- "TARGET_AVX"
+ "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"#"
"&& reload_completed"
[(const_int 0)]
(match_operand:VI4F_256 1 "nonimmediate_operand" "xm,x")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
- "TARGET_AVX"
+ "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"#"
"&& reload_completed"
[(const_int 0)]
(const_int 2) (const_int 3)
(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
- "TARGET_AVX"
+ "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"#"
"&& reload_completed"
[(const_int 0)]
(const_int 10) (const_int 11)
(const_int 12) (const_int 13)
(const_int 14) (const_int 15)])))]
- "TARGET_AVX"
+ "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"#"
"&& reload_completed"
[(const_int 0)]
(vec_select:SF
(match_operand:V4SF 1 "memory_operand" "o")
(parallel [(match_operand 2 "const_0_to_3_operand" "n")])))]
- ""
+ "TARGET_SSE"
"#"
- "reload_completed"
+ "&& reload_completed"
[(const_int 0)]
{
int i = INTVAL (operands[2]);
/* Extract the even bytes and merge them back together. */
ix86_expand_vec_extract_even_odd (operands[0], t[5], t[4], 0);
+
+ set_unique_reg_note (get_last_insn (), REG_EQUAL,
+ gen_rtx_MULT (V16QImode, operands[1], operands[2]));
DONE;
})
/* Merge the parts back together. */
emit_insn (gen_vec_interleave_lowv4si (op0, t5, t6));
+
+ set_unique_reg_note (get_last_insn (), REG_EQUAL,
+ gen_rtx_MULT (V4SImode, operands[1], operands[2]));
DONE;
})
emit_insn (gen_addv2di3 (t6, t1, t4));
emit_insn (gen_addv2di3 (op0, t6, t5));
}
+
+ set_unique_reg_note (get_last_insn (), REG_EQUAL,
+ gen_rtx_MULT (V2DImode, operands[1], operands[2]));
DONE;
})