arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS

As per the AXG datasheet add missing cache information to the Amlogic AXG
SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-5-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 2df143aa77ce3ca4f101ffe0c6ed83c6a3bc52c5..04fb130ac7c6a498f7e8029aeaa7e511cbfe815d 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -83,6 +83,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
                        dynamic-power-coefficient = <140>;
@@ -94,6 +100,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
                        dynamic-power-coefficient = <140>;
@@ -105,6 +117,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
                        dynamic-power-coefficient = <140>;
@@ -115,6 +133,9 @@
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;
+                       cache-size = <0x80000>; /* L2. 512 KB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };