arm64: dts: qcom: sm6115: declare VLS CLAMP register for USB3 PHY

[ Upstream commit 95d739ed962c9aaa17d77b739606dbdf31879f6e ]

The USB3 PHY on the SM6115 platform doesn't have built-in
PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately
via the register in the TCSR space. Declare corresponding register.

Fixes: 9dd5f6dba729 ("arm64: dts: qcom: sm6115: Add USB SS qmp phy node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240117-usbc-phy-vls-clamp-v2-6-a950c223f10f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index f9849b8befbf24b54992d49af812eaa94288c3fb..b627c473ffa54499b168e46b90b0cf39db9dceb6 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -614,6 +614,11 @@
                        #hwlock-cells = <1>;
                };
 
+               tcsr_regs: syscon@3c0000 {
+                       compatible = "qcom,sm6115-tcsr", "syscon";
+                       reg = <0x0 0x003c0000 0x0 0x40000>;
+               };
+
                tlmm: pinctrl@500000 {
                        compatible = "qcom,sm6115-tlmm";
                        reg = <0x0 0x00500000 0x0 0x400000>,
@@ -879,6 +884,8 @@
 
                        #phy-cells = <0>;
 
+                       qcom,tcsr-reg = <&tcsr_regs 0xb244>;
+
                        status = "disabled";
                };