arm64: dts: ti: k3-j721s2-som-p0: Add DSI to eDP

Add DT nodes for DSI to eDP bridge. The DSI to eDP bridge used is
SN65DSI86 on SOM.

Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Tested-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250716060114.52122-6-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 54fc5c4f8c3f521046d55d4366e6e7ae5f9e9dbd..a9dbe14fb0c96f1194591fd57880395bf3f836d0 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -152,6 +152,30 @@
                #phy-cells = <0>;
                max-bitrate = <5000000>;
        };
+
+       vsys_io_1v8: regulator-vsys-io-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "vsys_io_1v8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       vsys_io_1v2: regulator-vsys-io-1v2 {
+               compatible = "regulator-fixed";
+               regulator-name = "vsys_io_1v2";
+               regulator-min-microvolt = <1200000>;
+               regulator-max-microvolt = <1200000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       edp1_refclk: clock-edp1-refclk {
+               compatible = "fixed-clock";
+               clock-frequency = <19200000>;
+               #clock-cells = <0>;
+       };
 };
 
 &wkup_pmx0 {
@@ -630,3 +654,30 @@
        memory-region = <&c71_1_dma_memory_region>,
                        <&c71_1_memory_region>;
 };
+
+&main_i2c4 {
+       bridge_dsi_edp: bridge-dsi-edp@2c {
+               compatible = "ti,sn65dsi86";
+               reg = <0x2c>;
+               clock-names = "refclk";
+               clocks = <&edp1_refclk>;
+               enable-gpios = <&exp_som 5 0>;
+               vpll-supply = <&vsys_io_1v8>;
+               vccio-supply = <&vsys_io_1v8>;
+               vcca-supply = <&vsys_io_1v2>;
+               vcc-supply = <&vsys_io_1v2>;
+
+               dsi_edp_bridge_ports: ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+};