iio/adc/pac1934: fix channel disable configuration

There are two problems with the chip configuration in this driver:
- First, is that writing 12 bytes (ARRAY_SIZE(regs)) would anyhow
  lead to a config overflow due to HW auto increment implementation
  in the chip.
- Second, the i2c_smbus_write_block_data write ends up in writing
  unexpected value to the channel_dis register, this is because
  the smbus size that is 0x03 in this case gets written to the
  register. The PAC1931/2/3/4 data sheet does not really specify
  that block write is indeed supported.

This problem is probably not visible on PAC1934 version where all
channels are used as the chip is properly configured by luck,
but in our case whenusing PAC1931 this leads to nonfunctional device.

Fixes: 0fb528c8255b (iio: adc: adding support for PAC193x)
Suggested-by: Rene Straub <mailto:rene.straub@belden.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@belden.com>
Reviewed-by: Marius Cristea <marius.cristea@microchip.com>
Link: https://patch.msgid.link/20250811130904.2481790-1-aleksandar.gerasimovski@belden.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/adc/pac1934.c b/drivers/iio/adc/pac1934.c
index 09fe88eb3fb04578137403a020d9befaa75610a6..2e442e46f679738e6159dff4fb4ba978b1d2ff8a 100644 (file)
--- a/drivers/iio/adc/pac1934.c
+++ b/drivers/iio/adc/pac1934.c
@@ -88,6 +88,7 @@
 #define PAC1934_VPOWER_3_ADDR                  0x19
 #define PAC1934_VPOWER_4_ADDR                  0x1A
 #define PAC1934_REFRESH_V_REG_ADDR             0x1F
+#define PAC1934_SLOW_REG_ADDR                  0x20
 #define PAC1934_CTRL_STAT_REGS_ADDR            0x1C
 #define PAC1934_PID_REG_ADDR                   0xFD
 #define PAC1934_MID_REG_ADDR                   0xFE
@@ -1265,8 +1266,23 @@ static int pac1934_chip_configure(struct pac1934_chip_info *info)
        /* no SLOW triggered REFRESH, clear POR */
        regs[PAC1934_SLOW_REG_OFF] = 0;
 
-       ret =  i2c_smbus_write_block_data(client, PAC1934_CTRL_STAT_REGS_ADDR,
-                                         ARRAY_SIZE(regs), (u8 *)regs);
+       /*
+        * Write the three bytes sequentially, as the device does not support
+        * block write.
+        */
+       ret = i2c_smbus_write_byte_data(client, PAC1934_CTRL_STAT_REGS_ADDR,
+                                       regs[PAC1934_CHANNEL_DIS_REG_OFF]);
+       if (ret)
+               return ret;
+
+       ret = i2c_smbus_write_byte_data(client,
+                                       PAC1934_CTRL_STAT_REGS_ADDR + PAC1934_NEG_PWR_REG_OFF,
+                                       regs[PAC1934_NEG_PWR_REG_OFF]);
+       if (ret)
+               return ret;
+
+       ret = i2c_smbus_write_byte_data(client, PAC1934_SLOW_REG_ADDR,
+                                       regs[PAC1934_SLOW_REG_OFF]);
        if (ret)
                return ret;