#define SPI_FLASH_CFI_MFR_STMICRO 0x20
#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
#define SPI_FLASH_CFI_MFR_WINBOND 0xef
+#define SPI_FLASH_CFI_MFR_ISSI 0x9d
/* Erase commands */
#define CMD_ERASE_4K 0x20
{"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
{"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
{"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_ISSI
+ {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_EXTN | QUAD_IO_FAST, WR_QPP},
+ {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_EXTN | QUAD_IO_FAST, WR_QPP},
+ {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_EXTN | QUAD_IO_FAST, WR_QPP},
#endif
{}, /* Empty entry to terminate the list */
/*
CMD_READ_QUAD_IO_FAST,
};
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
{
u8 qeb_status;
static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
case SPI_FLASH_CFI_MFR_MACRONIX:
+ case SPI_FLASH_CFI_MFR_ISSI:
return spi_flash_set_qeb_mxic(flash);
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
flash->read_cmd = CMD_READ_DUAL_IO_FAST;
}
} else {
- /* Go for default supported read cmd */
- flash->read_cmd = CMD_READ_ARRAY_FAST;
+ if (idcode[0] == SPI_FLASH_CFI_MFR_ISSI)
+ flash->read_cmd = CMD_READ_QUAD_IO_FAST;
+ else
+ /* Go for default supported read cmd */
+ flash->read_cmd = CMD_READ_ARRAY_FAST;
}
/* Not require to look for fastest only two write cmds yet */
*/
switch (flash->read_cmd) {
case CMD_READ_QUAD_IO_FAST:
- flash->dummy_byte = 2;
+ if (idcode[0] == SPI_FLASH_CFI_MFR_ISSI)
+ flash->dummy_byte = 3;
+ else
+ flash->dummy_byte = 2;
break;
case CMD_READ_DUAL_IO_FAST:
if (idcode[0] == SPI_FLASH_CFI_MFR_STMICRO)