clk: tegra: Use correct parent for dpaux clock

The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 463c114358e657f98b05dfad92ff5266a681352b..d758f2169d418a5ffb89e1eca2233a1ce5b7bf90 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -821,7 +821,7 @@ static struct tegra_periph_init_data gate_clks[] = {
        GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
        GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
        GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
-       GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
+       GATE("dpaux", "pll_p", 181, 0, tegra_clk_dpaux, 0),
        GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
        GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
        GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),