--- /dev/null
+From 25c2a075eb6a3031813b6051bd10dfc22c36a2a4 Mon Sep 17 00:00:00 2001
+From: Herve Codina <herve.codina@bootlin.com>
+Date: Mon, 4 Jul 2022 12:28:43 +0200
+Subject: clk: lan966x: Fix the lan966x clock gate register address
+
+From: Herve Codina <herve.codina@bootlin.com>
+
+commit 25c2a075eb6a3031813b6051bd10dfc22c36a2a4 upstream.
+
+The register address used for the clock gate register is the base
+register address coming from first reg map (ie. the generic
+clock registers) instead of the second reg map defining the clock
+gate register.
+
+Use the correct clock gate register address.
+
+Fixes: 5ad5915dea00 ("clk: lan966x: Extend lan966x clock driver for clock gating support")
+Signed-off-by: Herve Codina <herve.codina@bootlin.com>
+Link: https://lore.kernel.org/r/20220704102845.168438-2-herve.codina@bootlin.com
+Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Tested-by: Michael Walle <michael@walle.cc>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/clk-lan966x.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/clk-lan966x.c
++++ b/drivers/clk/clk-lan966x.c
+@@ -213,7 +213,7 @@ static int lan966x_gate_clk_register(str
+
+ hw_data->hws[i] =
+ devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name,
+- "lan966x", 0, base,
++ "lan966x", 0, gate_base,
+ clk_gate_desc[idx].bit_idx,
+ 0, &clk_gate_lock);
+