]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths
authorKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tue, 12 Aug 2025 10:48:15 +0000 (12:48 +0200)
committerBjorn Andersson <andersson@kernel.org>
Mon, 1 Sep 2025 18:03:33 +0000 (13:03 -0500)
USB connector bindings describe a ports subnode, which describes how
its High-/SuperSpeed data lines (as well as the SBU pins for Type-C)
are connected.

On Linux, skipping the graph results in the 'connect_type' sysfs
attribute returning 'unknown', instead of 'hotplug' or similar. This in
turn is parsed by some operating systems (such as CrOS), to e.g. make
security policy decisions.

Define ports {} for the DWC controller & the QMPPHY and connect them
together for the SS lanes.

Leave the DP endpoint unconnected for now, as both Aspire 1 and the
Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
Take the creative liberty to add a newline before its ports' subnodes
though.

[1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/

Suggested-by: Rob Herring (Arm) <robh@kernel.org>
Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250812-topic-7180_qmpphy_ports-v2-1-7dc87e9a1f73@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/sc7180.dtsi

index 8f827f1d8515d6113c85a2ecacf7ac364e195242..a0df10a97c7f8aa5cd468c8983e74256490d1d06 100644 (file)
 
                        #clock-cells = <1>;
                        #phy-cells = <1>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+
+                                       usb_1_qmpphy_out: endpoint { };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+
+                                       usb_1_qmpphy_usb_ss_in: endpoint {
+                                               remote-endpoint = <&usb_1_dwc3_ss>;
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+
+                                       usb_1_qmpphy_dp_in: endpoint { };
+                               };
+                       };
                };
 
                pmu@90b6300 {
                                phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
                                phy-names = "usb2-phy", "usb3-phy";
                                maximum-speed = "super-speed";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               usb_1_dwc3_hs: endpoint {
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               usb_1_dwc3_ss: endpoint {
+                                                       remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+                                               };
+                                       };
+                               };
                        };
                };
 
                                ports {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
+
                                        port@0 {
                                                reg = <0>;
+
                                                dp_in: endpoint {
                                                        remote-endpoint = <&dpu_intf0_out>;
                                                };
 
                                        port@1 {
                                                reg = <1>;
+
                                                mdss_dp_out: endpoint { };
                                        };
                                };