Get rid of add with carry and subtract with borrow from the IR.

git-svn-id: svn://svn.valgrind.org/vex/trunk@92

diff --git a/VEX/priv/guest-x86/x86toIR.c b/VEX/priv/guest-x86/x86toIR.c
index d9f4ec5bb7c6bd28e0fa18053a522f18746f9f92..249cefa2c53e40e609194e89c5f8c9e607e312f2 100644 (file)
--- a/VEX/priv/guest-x86/x86toIR.c
+++ b/VEX/priv/guest-x86/x86toIR.c
@@ -326,7 +326,7 @@ static IROp mkSizedOp ( IRType ty, IROp op8 )
    Int adj;
    vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32);
    vassert(op8 == Iop_Add8 || op8 == Iop_Sub8 
-           || op8 == Iop_Adc8 || op8 == Iop_Sbb8 
+           // || op8 == Iop_Adc8 || op8 == Iop_Sbb8 
            || op8 == Iop_Mul8 
            || op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8
            || op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8
@@ -1921,7 +1921,6 @@ UInt dis_Grp1 ( UChar sorb,
                 UInt delta, UChar modrm, 
                 Int am_sz, Int d_sz, Int sz, UInt d32 )
 {
-   IROp    op8;
    Int     len;
    UChar   dis_buf[50];
    IRType  ty   = szToITy(sz);
@@ -1929,10 +1928,12 @@ UInt dis_Grp1 ( UChar sorb,
    IRTemp  src  = newTemp(ty);
    IRTemp  dst0 = newTemp(ty);
    IRTemp  addr = INVALID_IRTEMP;
+   IROp    op8  = Iop_INVALID;
 
    switch (gregOfRM(modrm)) {
       case 0: op8 = Iop_Add8; break;  case 1: op8 = Iop_Or8;  break;
-      case 2: op8 = Iop_Adc8; break;  //case 3: op8 = Iop_Sbb8; break;
+      case 2: break;  // ADC
+      case 3: break;  // SBB
       case 4: op8 = Iop_And8; break;  case 5: op8 = Iop_Sub8; break;
       case 6: op8 = Iop_Xor8; break;  case 7: op8 = Iop_Sub8; break;
       default: vpanic("dis_Grp1: unhandled case");
@@ -1940,7 +1941,7 @@ UInt dis_Grp1 ( UChar sorb,
 
    if (epartIsReg(modrm)) {
       vassert(am_sz == 1);
-      vassert(op8 != Iop_Adc8 && op8 != Iop_Sbb8);
+      vassert(op8 != Iop_INVALID);
 
       assign(dst0, getIReg(sz,eregOfRM(modrm)));
       assign(src,  mkU(ty,d32));
@@ -1960,10 +1961,10 @@ UInt dis_Grp1 ( UChar sorb,
       assign(dst0, loadLE(ty,mkexpr(addr)));
       assign(src, mkU(ty,d32));
 
-      if (op8 == Iop_Adc8) {
+      if (gregOfRM(modrm) == 2 /* ADC */) {
          helper_ADC( sz, dst1, dst0, src );
       } else 
-      if (op8 == Iop_Sbb8) {
+      if (gregOfRM(modrm) == 3 /* SBB */) {
          vassert(0);
       } else {
          assign(dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)));

diff --git a/VEX/priv/ir/ir_defs.c b/VEX/priv/ir/ir_defs.c
index 3794dbb23ad9b27ee35ef118967f6bdb32d6059f..658f996e259ffbb1311ee4f98acb3823f5f86eee 100644 (file)
--- a/VEX/priv/ir/ir_defs.c
+++ b/VEX/priv/ir/ir_defs.c
@@ -419,19 +419,19 @@ void typeOfPrimop ( IROp op, IRType* t_dst, IRType* t_arg1, IRType* t_arg2 )
    *t_arg1 = Ity_INVALID;
    *t_arg2 = Ity_INVALID;
    switch (op) {
-      case Iop_Add8: case Iop_Sub8: case Iop_Adc8: case Iop_Sbb8:
+      case Iop_Add8: case Iop_Sub8: //case Iop_Adc8: case Iop_Sbb8:
       case Iop_Mul8: case Iop_Or8:  case Iop_And8: case Iop_Xor8:
          BINARY(Ity_I8,Ity_I8,Ity_I8);
 
-      case Iop_Add16: case Iop_Sub16: case Iop_Adc16: case Iop_Sbb16:
+      case Iop_Add16: case Iop_Sub16: //case Iop_Adc16: case Iop_Sbb16:
       case Iop_Mul16: case Iop_Or16:  case Iop_And16: case Iop_Xor16:
          BINARY(Ity_I16,Ity_I16,Ity_I16);
 
-      case Iop_Add32: case Iop_Sub32: case Iop_Adc32: case Iop_Sbb32:
+      case Iop_Add32: case Iop_Sub32: //case Iop_Adc32: case Iop_Sbb32:
       case Iop_Mul32: case Iop_Or32:  case Iop_And32: case Iop_Xor32:
          BINARY(Ity_I32,Ity_I32,Ity_I32);
 
-      case Iop_Add64: case Iop_Sub64: case Iop_Adc64: case Iop_Sbb64:
+      case Iop_Add64: case Iop_Sub64: //case Iop_Adc64: case Iop_Sbb64:
       case Iop_Mul64: case Iop_Or64:  case Iop_And64: case Iop_Xor64:
          BINARY(Ity_I64,Ity_I64,Ity_I64);
 

diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h
index 7a42ed2b839bb2d7c65287a3b9d0f177a6c6382d..51901d4fe15343f7ab20c427c1e84f4b060b74db 100644 (file)
--- a/VEX/pub/libvex_ir.h
+++ b/VEX/pub/libvex_ir.h
@@ -69,11 +69,11 @@ typedef
    enum { 
       /* Do not change this ordering.  The IR generators
          rely on (eg) Iop_Add64 == IopAdd8 + 3. */
-      Iop_Add8=0x13000,  
-                 Iop_Add16,  Iop_Add32,  Iop_Add64,
+      Iop_INVALID=0x13000,
+      Iop_Add8,  Iop_Add16,  Iop_Add32,  Iop_Add64,
       Iop_Sub8,  Iop_Sub16,  Iop_Sub32,  Iop_Sub64,
-      Iop_Adc8,  Iop_Adc16,  Iop_Adc32,  Iop_Adc64,
-      Iop_Sbb8,  Iop_Sbb16,  Iop_Sbb32,  Iop_Sbb64,
+//Iop_Adc8,  Iop_Adc16,  Iop_Adc32,  Iop_Adc64,
+//Iop_Sbb8,  Iop_Sbb16,  Iop_Sbb32,  Iop_Sbb64,
       /* Signless mul.  MullS/MullU is elsewhere. */
       Iop_Mul8,  Iop_Mul16,  Iop_Mul32,  Iop_Mul64,
       Iop_Or8,   Iop_Or16,   Iop_Or32,   Iop_Or64,