drm/msm: Disable the RPTR shadow

commit f6828e0c4045f03f9cf2df6c2a768102641183f4 upstream.

Disable the RPTR shadow across all targets. It will be selectively
re-enabled later for targets that need it.

Cc: stable@vger.kernel.org
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
index 6021f8d9efd1fbb0230ee921da3a9cdac3095ef1..48fa49f69d6d0a2180afecdcd7327de5344b398e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -164,6 +164,11 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
        if (ret)
                return ret;
 
+       gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
+               MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
+
+       gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
+
        /* NOTE: PM4/micro-engine firmware registers look to be the same
         * for a2xx and a3xx.. we could possibly push that part down to
         * adreno_gpu base class.  Or push both PM4 and PFP but

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 0a5ea9f56cb886aba890fffe00c414942cf15a4b..f6471145a7a607db4984242fdee8aa1d2e5332fc 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -211,6 +211,16 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
        if (ret)
                return ret;
 
+       /*
+        * Use the default ringbuffer size and block size but disable the RPTR
+        * shadow
+        */
+       gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
+               MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
+
+       /* Set the ringbuffer address */
+       gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
+
        /* setup access protection: */
        gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);
 

diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index b9b26b2bf9c548d38b81347fb745d811ccf20db4..9547536006254721ed1e0f9963830c0f3867a276 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -267,6 +267,16 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
        if (ret)
                return ret;
 
+       /*
+        * Use the default ringbuffer size and block size but disable the RPTR
+        * shadow
+        */
+       gpu_write(gpu, REG_A4XX_CP_RB_CNTL,
+               MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
+
+       /* Set the ringbuffer address */
+       gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
+
        /* Load PM4: */
        ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data);
        len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4;

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 7d964d43cd7a242389834c8de0ef0e8b12866c22..1bf0969ce725f66cf85a7159dd4fce06cef6ed6d 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -702,8 +702,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
        if (ret)
                return ret;
 
-       a5xx_preempt_hw_init(gpu);
-
        if (!adreno_is_a510(adreno_gpu))
                a5xx_gpmu_ucode_init(gpu);
 
@@ -711,6 +709,15 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
        if (ret)
                return ret;
 
+       /* Set the ringbuffer address */
+       gpu_write64(gpu, REG_A5XX_CP_RB_BASE, REG_A5XX_CP_RB_BASE_HI,
+               gpu->rb[0]->iova);
+
+       gpu_write(gpu, REG_A5XX_CP_RB_CNTL,
+               MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
+
+       a5xx_preempt_hw_init(gpu);
+
        /* Disable the interrupts through the initial bringup stage */
        gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK);
 

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7768557cdfb2805aa8a7865603649c9bf8ba0742..b7dc350d96fc827417435a7c30a6b17c24b489d2 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -557,6 +557,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
        if (ret)
                goto out;
 
+       /* Set the ringbuffer address */
+       gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
+               gpu->rb[0]->iova);
+
+       gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
+               MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
+
        /* Always come up on rb 0 */
        a6xx_gpu->cur_ring = gpu->rb[0];
 

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index e7b39f3ca33dc3906cb0140f974bde97e2182ea7..a74ccc5b8220d3d9892f21ed4bfe7ab0a6c1dcac 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -400,26 +400,6 @@ int adreno_hw_init(struct msm_gpu *gpu)
                ring->memptrs->rptr = 0;
        }
 
-       /*
-        * Setup REG_CP_RB_CNTL.  The same value is used across targets (with
-        * the excpetion of A430 that disables the RPTR shadow) - the cacluation
-        * for the ringbuffer size and block size is moved to msm_gpu.h for the
-        * pre-processor to deal with and the A430 variant is ORed in here
-        */
-       adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
-               MSM_GPU_RB_CNTL_DEFAULT |
-               (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
-
-       /* Setup ringbuffer address - use ringbuffer[0] for GPU init */
-       adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
-               REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
-
-       if (!adreno_is_a430(adreno_gpu)) {
-               adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
-                       REG_ADRENO_CP_RB_RPTR_ADDR_HI,
-                       rbmemptr(gpu->rb[0], rptr));
-       }
-
        return 0;
 }
 
@@ -427,11 +407,8 @@ int adreno_hw_init(struct msm_gpu *gpu)
 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
                struct msm_ringbuffer *ring)
 {
-       if (adreno_is_a430(adreno_gpu))
-               return ring->memptrs->rptr = adreno_gpu_read(
-                       adreno_gpu, REG_ADRENO_CP_RB_RPTR);
-       else
-               return ring->memptrs->rptr;
+       return ring->memptrs->rptr = adreno_gpu_read(
+               adreno_gpu, REG_ADRENO_CP_RB_RPTR);
 }
 
 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)