xilinx: ultrascale: Define GICC_BASE and GICD_BASE in config file

Define GICC_BASE and GICD_BASE in config file in board config file
to avoid compilation errors.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/include/asm/arch-ultrascale/hardware.h b/arch/arm/include/asm/arch-ultrascale/hardware.h
index 04074a0a445cf2658eae1cd86ba49adab19a6fa8..ed56f45453a08c08851a4a74dad90c053f7f8a11 100644 (file)
--- a/arch/arm/include/asm/arch-ultrascale/hardware.h
+++ b/arch/arm/include/asm/arch-ultrascale/hardware.h
@@ -8,10 +8,6 @@
 #ifndef _ASM_ARCH_HARDWARE_H
 #define _ASM_ARCH_HARDWARE_H
 
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE      0xFD3FF000
-#define GICC_BASE      0xFD3FE100
-
 #define ZYNQ_SERIAL_BASEADDR0  0xFF000000
 #define ZYNQ_SERIAL_BASEADDR1  0xFF001000
 

diff --git a/board/xilinx/ultrascale/ultrascale.c b/board/xilinx/ultrascale/ultrascale.c
index 61539acd6545721f368cc31f47f43ee52ae40aed..c26bf85a672635317df0c91c885ae5658b569b0f 100644 (file)
--- a/board/xilinx/ultrascale/ultrascale.c
+++ b/board/xilinx/ultrascale/ultrascale.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;

diff --git a/include/configs/xilinx_ultrascale.h b/include/configs/xilinx_ultrascale.h
index 70940f924c1f1a6cbde179dfb7ed6d0b58b464c7..c0fe01b16c41d123a60a56a2730a8010ac0a107b 100644 (file)
--- a/include/configs/xilinx_ultrascale.h
+++ b/include/configs/xilinx_ultrascale.h
@@ -11,8 +11,6 @@
 #ifndef __XILINX_ULTRASCALE_H
 #define __XILINX_ULTRASCALE_H
 
-#include <asm/arch/hardware.h>
-
 #define CONFIG_REMAKE_ELF
 
 /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
@@ -21,6 +19,10 @@
 
 #define XILINX_ULTRASCALE
 
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE      0xFD3FF000
+#define GICC_BASE      0xFD3FE100
+
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0