4.9-stable patches

added patches:
	revert-net-axienet-wait-for-phyrstcmplt-after-core-reset.patch

diff --git a/queue-4.9/revert-net-axienet-wait-for-phyrstcmplt-after-core-reset.patch b/queue-4.9/revert-net-axienet-wait-for-phyrstcmplt-after-core-reset.patch
new file mode 100644 (file)
index 0000000..144daf5
--- /dev/null
+++ b/queue-4.9/revert-net-axienet-wait-for-phyrstcmplt-after-core-reset.patch
@@ -0,0 +1,52 @@
+From guillaume.bertholon@ens.fr  Fri Feb 11 15:29:11 2022
+From: Guillaume Bertholon <guillaume.bertholon@ens.fr>
+Date: Fri, 11 Feb 2022 14:33:01 +0100
+Subject: Revert "net: axienet: Wait for PhyRstCmplt after core reset"
+To: gregkh@linuxfoundation.org
+Cc: guillaume.bertholon@ens.fr, stable@vger.kernel.org
+Message-ID: <1644586381-5078-1-git-send-email-guillaume.bertholon@ens.fr>
+
+From: Guillaume Bertholon <guillaume.bertholon@ens.fr>
+
+This reverts commit 9f1a3c13342b4d96b9baa337ec5fb7d453828709.
+
+The upstream commit b400c2f4f4c5 ("net: axienet: Wait for PhyRstCmplt
+after core reset") add new instructions in the `__axienet_device_reset`
+function to wait until PhyRstCmplt bit is set, and return a non zero-exit
+value if this exceeds a timeout.
+
+However, its backported version in 4.9 (commit 9f1a3c13342b ("net:
+axienet: Wait for PhyRstCmplt after core reset")) insert these
+instructions in `axienet_dma_bd_init` instead.
+
+Unlike upstream, the version of `__axienet_device_reset` currently present
+in branch stable/linux-4.9.y does not return an integer for error codes.
+Therefore fixing the backport cannot be as simple as moving the inserted
+instructions in the right place, and we simply revert it instead.
+
+Fixes: 9f1a3c13342b ("net: axienet: Wait for PhyRstCmplt after core reset")
+Signed-off-by: Guillaume Bertholon <guillaume.bertholon@ens.fr>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/xilinx/xilinx_axienet_main.c |   10 ----------
+ 1 file changed, 10 deletions(-)
+
+--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+@@ -278,16 +278,6 @@ static int axienet_dma_bd_init(struct ne
+       axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
+                         cr | XAXIDMA_CR_RUNSTOP_MASK);
+ 
+-      /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */
+-      ret = read_poll_timeout(axienet_ior, value,
+-                              value & XAE_INT_PHYRSTCMPLT_MASK,
+-                              DELAY_OF_ONE_MILLISEC, 50000, false, lp,
+-                              XAE_IS_OFFSET);
+-      if (ret) {
+-              dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__);
+-              return ret;
+-      }
+-
+       return 0;
+ out:
+       axienet_dma_bd_release(ndev);

diff --git a/queue-4.9/series b/queue-4.9/series
index 1576221f1c6ff7a3bb225b879e1098a93b2bdfc8..68ba494770d279450c2f01312e289a3d2bdf1ceb 100644 (file)
--- a/queue-4.9/series
+++ b/queue-4.9/series
@@ -5,3 +5,4 @@ nfsd-clamp-write-offsets.patch
 input-i8042-fix-misplaced-backport-of-add-asus-zenbook-flip-to-noselftest-list.patch
 serial-sh-sci-fix-misplaced-backport-of-fix-late-enablement-of-autorts.patch
 alsa-line6-fix-misplaced-backport-of-fix-wrong-altsetting-for-line6_podhd500_1.patch
+revert-net-axienet-wait-for-phyrstcmplt-after-core-reset.patch