.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_pc.c
:doc: GuC Power Conservation (PC)
+.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_rc.c
+ :doc: GuC Render C-states (GuC RC)
+
PCIe Gen5 Limitations
=====================
xe_guc_log.o \
xe_guc_pagefault.o \
xe_guc_pc.o \
+ xe_guc_rc.o \
xe_guc_submit.o \
xe_guc_tlb_inval.o \
xe_heci_gsc.o \
if (IS_SRIOV_PF(gt_to_xe(gt)))
xe_gt_sriov_pf_stop_prepare(gt);
- xe_uc_gucrc_disable(>->uc);
xe_uc_stop_prepare(>->uc);
xe_pagefault_reset(gt_to_xe(gt), gt);
#include "xe_guc_klv_helpers.h"
#include "xe_guc_log.h"
#include "xe_guc_pc.h"
+#include "xe_guc_rc.h"
#include "xe_guc_relay.h"
#include "xe_guc_submit.h"
#include "xe_memirq.h"
if (ret)
return ret;
+ ret = xe_guc_rc_init(guc);
+ if (ret)
+ return ret;
+
ret = xe_guc_engine_activity_init(guc);
if (ret)
return ret;
if (!IS_SRIOV_VF(guc_to_xe(guc))) {
int err;
+ xe_guc_rc_disable(guc);
err = xe_guc_pc_stop(&guc->pc);
xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n",
ERR_PTR(err));
* Render-C states is also a GuC PC feature that is now enabled in Xe for
* all platforms.
*
+ * Implementation details:
+ * -----------------------
+ * The implementation for GuC Power Management features is split as follows:
+ *
+ * xe_guc_rc: Logic for handling GuC RC
+ * xe_gt_idle: Host side logic for RC6 and Coarse Power gating (CPG)
+ * xe_guc_pc: Logic for all other SLPC related features
+ *
+ * There is some cross interaction between these where host C6 will need to be
+ * enabled when we plan to skip GuC RC. Also, the GuC RC mode is currently
+ * overridden through 0x3003 which is an SLPC H2G call.
*/
static struct xe_guc *pc_to_guc(struct xe_guc_pc *pc)
return ret;
}
-static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode)
-{
- struct xe_guc_ct *ct = pc_to_ct(pc);
- u32 action[] = {
- GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
- mode,
- };
- int ret;
-
- ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);
- if (ret && !(xe_device_wedged(pc_to_xe(pc)) && ret == -ECANCELED))
- xe_gt_err(pc_to_gt(pc), "GuC RC enable mode=%u failed: %pe\n",
- mode, ERR_PTR(ret));
- return ret;
-}
-
static u32 decode_freq(u32 raw)
{
return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
return ret;
}
-/**
- * xe_guc_pc_gucrc_disable - Disable GuC RC
- * @pc: Xe_GuC_PC instance
- *
- * Disables GuC RC by taking control of RC6 back from GuC.
- *
- * Return: 0 on success, negative error code on error.
- */
-int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc)
-{
- struct xe_device *xe = pc_to_xe(pc);
- struct xe_gt *gt = pc_to_gt(pc);
- int ret = 0;
-
- if (xe->info.skip_guc_pc)
- return 0;
-
- ret = pc_action_setup_gucrc(pc, GUCRC_HOST_CONTROL);
- if (ret)
- return ret;
-
- return xe_gt_idle_disable_c6(gt);
-}
-
/**
* xe_guc_pc_override_gucrc_mode - override GUCRC mode
* @pc: Xe_GuC_PC instance
return -ETIMEDOUT;
if (xe->info.skip_guc_pc) {
- if (xe->info.platform != XE_PVC)
- xe_gt_idle_enable_c6(gt);
-
/* Request max possible since dynamic freq mgmt is not enabled */
pc_set_cur_freq(pc, UINT_MAX);
return 0;
if (ret)
return ret;
- if (xe->info.platform == XE_PVC) {
- xe_guc_pc_gucrc_disable(pc);
- return 0;
- }
-
- ret = pc_action_setup_gucrc(pc, GUCRC_FIRMWARE_CONTROL);
- if (ret)
- return ret;
-
/* Enable SLPC Optimized Strategy for compute */
ret = pc_action_set_strategy(pc, SLPC_OPTIMIZED_STRATEGY_COMPUTE);
{
struct xe_device *xe = pc_to_xe(pc);
- if (xe->info.skip_guc_pc) {
- xe_gt_idle_disable_c6(pc_to_gt(pc));
+ if (xe->info.skip_guc_pc)
return 0;
- }
mutex_lock(&pc->freq_lock);
pc->freq_ready = false;
return;
CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL);
- xe_guc_pc_gucrc_disable(pc);
XE_WARN_ON(xe_guc_pc_stop(pc));
/* Bind requested freq to mert_freq_cap before unload */
int xe_guc_pc_init(struct xe_guc_pc *pc);
int xe_guc_pc_start(struct xe_guc_pc *pc);
int xe_guc_pc_stop(struct xe_guc_pc *pc);
-int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc);
int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode);
int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p);
--- /dev/null
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <drm/drm_print.h>
+
+#include "abi/guc_actions_slpc_abi.h"
+#include "xe_device.h"
+#include "xe_force_wake.h"
+#include "xe_gt.h"
+#include "xe_gt_idle.h"
+#include "xe_gt_printk.h"
+#include "xe_guc.h"
+#include "xe_guc_ct.h"
+#include "xe_guc_rc.h"
+#include "xe_pm.h"
+
+/**
+ * DOC: GuC RC (Render C-states)
+ *
+ * GuC handles the GT transition to deeper C-states in conjunction with Pcode.
+ * GuC RC can be enabled independently of the frequency component in SLPC,
+ * which is also controlled by GuC.
+ *
+ * This file will contain all H2G related logic for handling Render C-states.
+ * There are some calls to xe_gt_idle, where we enable host C6 when GuC RC is
+ * skipped. GuC RC is mostly independent of xe_guc_pc with the exception of
+ * functions that override the mode for which we have to rely on the SLPC H2G
+ * calls.
+ */
+
+static int guc_action_setup_gucrc(struct xe_guc *guc, u32 control)
+{
+ u32 action[] = {
+ GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,
+ control,
+ };
+ int ret;
+
+ ret = xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
+ if (ret && !(xe_device_wedged(guc_to_xe(guc)) && ret == -ECANCELED))
+ xe_gt_err(guc_to_gt(guc),
+ "GuC RC setup %s(%u) failed (%pe)\n",
+ control == GUCRC_HOST_CONTROL ? "HOST_CONTROL" :
+ control == GUCRC_FIRMWARE_CONTROL ? "FIRMWARE_CONTROL" :
+ "UNKNOWN", control, ERR_PTR(ret));
+ return ret;
+}
+
+/**
+ * xe_guc_rc_disable() - Disable GuC RC
+ * @guc: Xe GuC instance
+ *
+ * Disables GuC RC by taking control of RC6 back from GuC.
+ */
+void xe_guc_rc_disable(struct xe_guc *guc)
+{
+ struct xe_device *xe = guc_to_xe(guc);
+ struct xe_gt *gt = guc_to_gt(guc);
+
+ if (!xe->info.skip_guc_pc && xe->info.platform != XE_PVC)
+ if (guc_action_setup_gucrc(guc, GUCRC_HOST_CONTROL))
+ return;
+
+ xe_gt_WARN_ON(gt, xe_gt_idle_disable_c6(gt));
+}
+
+static void xe_guc_rc_fini_hw(void *arg)
+{
+ struct xe_guc *guc = arg;
+ struct xe_device *xe = guc_to_xe(guc);
+ struct xe_gt *gt = guc_to_gt(guc);
+
+ if (xe_device_wedged(xe))
+ return;
+
+ CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
+ xe_guc_rc_disable(guc);
+}
+
+/**
+ * xe_guc_rc_init() - Init GuC RC
+ * @guc: Xe GuC instance
+ *
+ * Add callback action for GuC RC
+ *
+ * Return: 0 on success, negative error code on error.
+ */
+int xe_guc_rc_init(struct xe_guc *guc)
+{
+ struct xe_device *xe = guc_to_xe(guc);
+ struct xe_gt *gt = guc_to_gt(guc);
+
+ xe_gt_assert(gt, xe_device_uc_enabled(xe));
+
+ return devm_add_action_or_reset(xe->drm.dev, xe_guc_rc_fini_hw, guc);
+}
+
+/**
+ * xe_guc_rc_enable() - Enable GuC RC feature if applicable
+ * @guc: Xe GuC instance
+ *
+ * Enables GuC RC feature.
+ *
+ * Return: 0 on success, negative error code on error.
+ */
+int xe_guc_rc_enable(struct xe_guc *guc)
+{
+ struct xe_device *xe = guc_to_xe(guc);
+ struct xe_gt *gt = guc_to_gt(guc);
+
+ xe_gt_assert(gt, xe_device_uc_enabled(xe));
+
+ CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
+ if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT))
+ return -ETIMEDOUT;
+
+ if (xe->info.platform == XE_PVC) {
+ xe_guc_rc_disable(guc);
+ return 0;
+ }
+
+ if (xe->info.skip_guc_pc) {
+ xe_gt_idle_enable_c6(gt);
+ return 0;
+ }
+
+ return guc_action_setup_gucrc(guc, GUCRC_FIRMWARE_CONTROL);
+}
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_GUC_RC_H_
+#define _XE_GUC_RC_H_
+
+struct xe_guc;
+
+int xe_guc_rc_init(struct xe_guc *guc);
+int xe_guc_rc_enable(struct xe_guc *guc);
+void xe_guc_rc_disable(struct xe_guc *guc);
+
+#endif
#include "xe_gt_sriov_vf.h"
#include "xe_guc.h"
#include "xe_guc_pc.h"
+#include "xe_guc_rc.h"
#include "xe_guc_engine_activity.h"
#include "xe_huc.h"
#include "xe_sriov.h"
if (ret)
goto err_out;
+ ret = xe_guc_rc_enable(&uc->guc);
+ if (ret)
+ goto err_out;
+
xe_guc_engine_activity_enable_stats(&uc->guc);
/* We don't fail the driver load if HuC fails to auth */
return xe_guc_reset_prepare(&uc->guc);
}
-void xe_uc_gucrc_disable(struct xe_uc *uc)
-{
- XE_WARN_ON(xe_guc_pc_gucrc_disable(&uc->guc.pc));
-}
-
void xe_uc_stop_prepare(struct xe_uc *uc)
{
xe_gsc_stop_prepare(&uc->gsc);
int xe_uc_init(struct xe_uc *uc);
int xe_uc_init_post_hwconfig(struct xe_uc *uc);
int xe_uc_load_hw(struct xe_uc *uc);
-void xe_uc_gucrc_disable(struct xe_uc *uc);
int xe_uc_reset_prepare(struct xe_uc *uc);
void xe_uc_runtime_resume(struct xe_uc *uc);
void xe_uc_runtime_suspend(struct xe_uc *uc);
projects / thirdparty / linux.git / commitdiff
