4.19-stable patches

added patches:
	arm64-cpufeature-fix-the-visibility-of-compat-hwcaps.patch

diff --git a/queue-4.19/arm64-cpufeature-fix-the-visibility-of-compat-hwcaps.patch b/queue-4.19/arm64-cpufeature-fix-the-visibility-of-compat-hwcaps.patch
new file mode 100644 (file)
index 0000000..21cfee4
--- /dev/null
+++ b/queue-4.19/arm64-cpufeature-fix-the-visibility-of-compat-hwcaps.patch
@@ -0,0 +1,121 @@
+From 85f1506337f0c79a4955edfeee86a18628e3735f Mon Sep 17 00:00:00 2001
+From: Amit Daniel Kachhap <amit.kachhap@arm.com>
+Date: Thu, 3 Nov 2022 13:52:32 +0530
+Subject: arm64: cpufeature: Fix the visibility of compat hwcaps
+
+From: Amit Daniel Kachhap <amit.kachhap@arm.com>
+
+commit 85f1506337f0c79a4955edfeee86a18628e3735f upstream.
+
+Commit 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the
+sysreg visible to user-space") forced the hwcaps to use sanitised
+user-space view of the id registers. However, the ID register structures
+used to select few compat cpufeatures (vfp, crc32, ...) are masked and
+hence such hwcaps do not appear in /proc/cpuinfo anymore for PER_LINUX32
+personality.
+
+Add the ID register structures explicitly and set the relevant entry as
+visible. As these ID registers are now of type visible so make them
+available in 64-bit userspace by making necessary changes in register
+emulation logic and documentation.
+
+While at it, update the comment for structure ftr_generic_32bits[] which
+lists the ID register that use it.
+
+Fixes: 237405ebef58 ("arm64: cpufeature: Force HWCAP to be based on the sysreg visible to user-space")
+Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
+Reviewed-by: James Morse <james.morse@arm.com>
+Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
+Link: https://lore.kernel.org/r/20221103082232.19189-1-amit.kachhap@arm.com
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/kernel/cpufeature.c |   42 ++++++++++++++++++++++++++++++++---------
+ 1 file changed, 33 insertions(+), 9 deletions(-)
+
+--- a/arch/arm64/kernel/cpufeature.c
++++ b/arch/arm64/kernel/cpufeature.c
+@@ -274,6 +274,30 @@ static const struct arm64_ftr_bits ftr_i
+       ARM64_FTR_END,
+ };
+ 
++static const struct arm64_ftr_bits ftr_mvfr0[] = {
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0),
++      ARM64_FTR_END,
++};
++
++static const struct arm64_ftr_bits ftr_mvfr1[] = {
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0),
++      ARM64_FTR_END,
++};
++
+ static const struct arm64_ftr_bits ftr_mvfr2[] = {
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
+@@ -289,10 +313,10 @@ static const struct arm64_ftr_bits ftr_d
+ 
+ static const struct arm64_ftr_bits ftr_id_isar5[] = {
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
+-      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
+-      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
+-      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
+-      ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
++      ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
+       ARM64_FTR_END,
+ };
+@@ -332,7 +356,7 @@ static const struct arm64_ftr_bits ftr_z
+  * Common ftr bits for a 32bit register with all hidden, strict
+  * attributes, with 4bit feature fields and a default safe value of
+  * 0. Covers the following 32bit registers:
+- * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
++ * id_isar[1-3], id_mmfr[1-3]
+  */
+ static const struct arm64_ftr_bits ftr_generic_32bits[] = {
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
+@@ -387,8 +411,8 @@ static const struct __ftr_reg_entry {
+       ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
+ 
+       /* Op1 = 0, CRn = 0, CRm = 3 */
+-      ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
+-      ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
++      ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
++      ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
+       ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
+ 
+       /* Op1 = 0, CRn = 0, CRm = 4 */
+@@ -1887,7 +1911,7 @@ cpufeature_pan_not_uao(const struct arm6
+ 
+ /*
+  * We emulate only the following system register space.
+- * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
++ * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
+  * See Table C5-6 System instruction encodings for System register accesses,
+  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
+  */
+@@ -1897,7 +1921,7 @@ static inline bool __attribute_const__ i
+               sys_reg_CRn(id) == 0x0 &&
+               sys_reg_Op1(id) == 0x0 &&
+               (sys_reg_CRm(id) == 0 ||
+-               ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
++               ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
+ }
+ 
+ /*

diff --git a/queue-4.19/series b/queue-4.19/series
index 7b659a4ee65aa6f030d9ac4bcb67dabce65c25a3..bd8194ebec7728da8f60c7726c05972c8fcdfc27 100644 (file)
--- a/queue-4.19/series
+++ b/queue-4.19/series
@@ -190,3 +190,4 @@ netfilter-nf_tables-set-element-extended-ack-reporting-support.patch
 netfilter-nf_tables-use-timestamp-to-check-for-set-element-timeout.patch
 netfilter-nf_tables-prefer-nft_chain_validate.patch
 drm-i915-gem-fix-virtual-memory-mapping-boundaries-calculation.patch
+arm64-cpufeature-fix-the-visibility-of-compat-hwcaps.patch