arm64: dts: imx8mm-phycore-som: optimize drive strengh

Reduce ENET pin drive strength from X6 to X4 to optimize signal
quality and reduce potential signal integrity issues.

Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
index 672baba4c8d0527f2de002d49aa96d30a6ae2373..921a7f58fd41da0967c03bf07620ca9a84075505 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
@@ -340,10 +340,10 @@
                        MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x90
                        MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x16
                        MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x16
-                       MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x16
-                       MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x16
-                       MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x16
-                       MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x16
+                       MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x12
+                       MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x12
+                       MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x12
+                       MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x12
                        MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7               0x10
                >;
        };