.intr_detection_width = -1, \
}
-#define QUP_I3C(qup_mode, qup_offset) \
- { \
- .mode = qup_mode, \
- .offset = qup_offset, \
- }
-
#define QUP_I3C_6_MODE_OFFSET 0xaf000
#define QUP_I3C_7_MODE_OFFSET 0xb0000
#define QUP_I3C_13_MODE_OFFSET 0xb1000
.intr_detection_width = -1, \
}
-#define UFS_RESET(pg_name, offset) \
- { \
- .grp = PINCTRL_PINGROUP(#pg_name, \
- pg_name##_pins, \
- ARRAY_SIZE(pg_name##_pins)), \
- .ctl_reg = offset, \
- .io_reg = offset + 0x4, \
- .intr_cfg_reg = 0, \
- .intr_status_reg = 0, \
- .mux_bit = -1, \
- .pull_bit = 3, \
- .drv_bit = 0, \
- .oe_bit = -1, \
- .in_bit = -1, \
- .out_bit = 0, \
- .intr_enable_bit = -1, \
- .intr_status_bit = -1, \
- .intr_target_bit = -1, \
- .intr_raw_status_bit = -1, \
- .intr_polarity_bit = -1, \
- .intr_detection_bit = -1, \
- .intr_detection_width = -1, \
- }
-
static const struct pinctrl_pin_desc qdu1000_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
.intr_detection_width = -1, \
}
-#define QUP_I3C(qup_mode, qup_offset) \
- { \
- .mode = qup_mode, \
- .offset = qup_offset, \
- }
-
#define QUP_I3C_6_MODE_OFFSET 0xAF000
#define QUP_I3C_7_MODE_OFFSET 0xB0000
#define QUP_I3C_13_MODE_OFFSET 0xB1000