drm/amd/display: move dcn42 bw_params init

Move it out of smu present block for cases where it isn't

Reviewed-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index df904b6fafe987529b133c916576eb3c45070008..a0296d5f0102f96eab9e1af231260454b825bc0d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -1138,11 +1138,6 @@ void dcn42_clk_mgr_construct(
                        dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1;
                        clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base);
                        clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base);
-
-                       clk_mgr->base.base.bw_params = &dcn42_bw_params;
-
-                       if (clk_mgr->base.smu_present)
-                               dcn42_get_smu_clocks(&clk_mgr->base);
                }
                /* in case we don't get a value from the BIOS, use default */
                if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
@@ -1155,6 +1150,10 @@ void dcn42_clk_mgr_construct(
        /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
 
        dcn42_read_ss_info_from_lut(&clk_mgr->base);
+
+       clk_mgr->base.base.bw_params = &dcn42_bw_params;
+       if (clk_mgr->base.smu_present)
+               dcn42_get_smu_clocks(&clk_mgr->base);
 }
 
 void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)